7.1.4. Breakpoint unit

The Cortex-M0+ BPU implementation provides between zero and four breakpoint registers. A processor configured with zero breakpoints implements no breakpoint functionality and the ROM table shows that no BPU is implemented.

BPU functionality

The processor breakpoints implement PC based breakpoint functionality, as described in the ARMv6-M Architecture Reference Manual.

BPU CoreSight identification

Table 7.5 shows the BPU identification registers and their values for debugger detection.

Table 7.5. BPU identification registers

Peripheral ID40x00000004Component and Peripheral ID register formats in the ARMv6-M Architecture Reference Manual.
Peripheral ID00x0000000B
Peripheral ID10x000000B0
Peripheral ID20x0000000B
Peripheral ID30x00000000
Component ID00x0000000D
Component ID10x000000E0
Component ID20x00000005
Component ID30x000000B1

See the ARMv6-M Architecture Reference Manual and the CoreSight SoC Technical Reference Manual for more information about the BPU CoreSight identification registers, and their addresses and access types.

Copyright © 2012 ARM. All rights reserved.ARM DDI 0484C