7.1.2. System Control Space

If debug is implemented, the processor provides debug through registers in the SCS, see Debug register summary.

SCS CoreSight identification

Table 7.3 shows the SCS CoreSight identification registers and values for debugger detection. Final debugger identification of the Cortex-M0+ processor is through the CPUID register in the SCS, see CPUID Register.

Table 7.3. SCS identification values

Peripheral ID40x00000004Component and Peripheral ID register formats in the ARMv6-M Architecture Reference Manual.
Peripheral ID00x00000008
Peripheral ID10x000000B0
Peripheral ID20x0000000B
Peripheral ID30x00000000
Component ID00x0000000D
Component ID10x000000E0
Component ID20x00000005
Component ID30x000000B1

See the ARMv6-M Architecture Reference Manual and the CoreSight SoC Technical Reference Manual for more information about the SCS CoreSight identification registers, and their addresses and access types.

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