7.1.1. Cortex-M0+ ROM table identification and entries

Table 7.1 shows the ROM table identification registers and values for debugger detection. This enables debuggers to identify the processor and its debug capabilities.


The Cortex-M0+ ROM table only supports word size transactions.

Table 7.1. Cortex-M0+ ROM table identification values

Peripheral ID40x00000004Component and peripheral ID register formats in the ARMv6-M Architecture Reference Manual.
Peripheral ID00x000000C0
Peripheral ID10x000000B4
Peripheral ID20x0000000B
Peripheral ID30x00000000
Component ID00x0000000D
Component ID10x00000010
Component ID20x00000005
Component ID30x000000B1

Table 7.2 shows the CoreSight components that the Cortex-M0+ ROM table points to. The values depend on the implemented debug configuration.

Table 7.2. Cortex-M0+ ROM table components

SCS0xFFF0F003See System Control Space.
DWT0xFFF02003[a]See Data watchpoint unit.
BPU0xFFF03003[b]See Breakpoint unit.
End marker0x00000000See DAP accessible ROM table in the ARMv6-M Architecture Reference Manual.
MemType0x00000001See CoreSight management registers in the ARMv6-M Architecture Reference Manual.

[a] Reads as 0xFFF02002 if no watchpoints are implemented.

[b] Reads as 0xFFF03002 if no breakpoints are implemented.

The SCS, DWT, and BPU ROM table entries point to the debug components at addresses 0xE000E000, 0xE0001000 and 0xE0002000 respectively. The value for each entry is the offset of that component from the ROM table base address, 0xE00FF000.

See the ARMv6-M Architecture Reference Manual and the CoreSight SoC Technical Reference Manual for more information about the ROM table ID and component registers, and their addresses and access types.

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