7.1.3. Data watchpoint unit

The Cortex-M0+ DWT implementation provides zero, one or two watchpoint register sets. A processor configured with zero watchpoint implements no watchpoint functionality and the ROM table shows that no DWT is implemented.

DWT functionality

The processor watchpoints implement both data address and PC based watchpoint functionality, a PC sampling register, and support comparator address masking, as described in the ARMv6-M Architecture Reference Manual.

DWT CoreSight identification

Table 7.4 shows the DWT identification registers and values for debugger detection.

Table 7.4. DWT identification values

Peripheral ID40x00000004Component and Peripheral ID register formats in the ARMv6-M Architecture Reference Manual.
Peripheral ID00x0000000A
Peripheral ID10x000000B0
Peripheral ID20x0000000B
Peripheral ID30x00000000
Component ID00x0000000D
Component ID10x000000E0
Component ID20x00000005
Component ID30x000000B1

See the ARMv6-M Architecture Reference Manual and the CoreSight SoC Technical Reference Manual for more information about the DWT CoreSight identification registers, and their addresses and access types.

DWT Program Counter Sample Register

A processor that implements the data watchpoint unit also implements the ARMv6-M optional DWT Program Counter Sample Register (DWT_PCSR). This register enables a debugger to periodically sample the PC without halting the processor. This provides coarse grained profiling. See the ARMv6-M Architecture Reference Manual for more information.

The Cortex-M0+ DWT_PCSR records both instructions that pass their condition codes and those that fail.

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