7.1. About debug

The processor implementation determines the debug configuration, including whether debug is implemented. If debug is not implemented, no ROM table is present and the halt, breakpoint, and watchpoint functionality is not present.

Basic debug functionality includes processor halt, single-step, processor core register access, Reset and HardFault Vector Catch, unlimited software breakpoints, and full system memory access. See the ARMv6-M Architecture Reference Manual.The debug option might include either or both:

The processor implementation can be partitioned to place the debug components in a separate power domain from the processor core and NVIC.

When debug is implemented, ARM recommends that a debugger identifies and connects to the debug components using the CoreSight debug infrastructure.

To discover the components in the CoreSight debug infrastructure, ARM recommends that a debugger follows the flow shown in Figure 7.1. In this example, a debugger reads the peripheral and component ID registers for each CoreSight component in the CoreSight system.

Figure 7.1. CoreSight discovery

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To identify the Cortex-M0+ processor within the CoreSight system, ARM recommends that a debugger:

  1. Locates and identifies the Cortex-M0+ ROM table using its CoreSight identification. See Table 7.1.

  2. Follows the pointers in that Cortex-M0+ ROM table:

    1. System Control Space (SCS).

    2. Breakpoint unit (BPU).

    3. Data watchpoint unit (DWT).

    See Table 7.2.

    When a debugger identifies the SCS from its CoreSight identification, it can identify the processor and its revision number from the CPUID register offset at 0xD00 in the SCS, 0xE000ED00.

A debugger cannot rely on the Cortex-M0+ ROM table being the first ROM table encountered. One or more system ROM tables are required between the access port and the Cortex-M0+ ROM table if other CoreSight components are in the system, or if the implementation is to be uniquely identifiable.

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