3.3. Instruction set summary

The processor implements the ARMv6-M Thumb instruction set, including a number of 32-bit instructions that use Thumb-2 technology. The ARMv6-M instruction set comprises:

Table 3.1 shows the Cortex-M0+ instructions and their cycle counts. The cycle counts are based on a system with zero wait-states.

Table 3.1. Cortex-M0+ instruction summary

Operation DescriptionAssembler Cycles
Move8-bit immediateMOVS Rd, #<imm>1
Lo to LoMOVS Rd, Rm1
Any to AnyMOV Rd, Rm1
Any to PCMOV PC, Rm2
Add3-bit immediateADDS Rd, Rn, #<imm>1
All registers LoADDS Rd, Rn, Rm1
Any to AnyADD Rd, Rd, Rm1
Any to PCADD PC, PC, Rm2
8-bit immediateADDS Rd, Rd, #<imm>1
With carryADCS Rd, Rd, Rm1
Immediate to SPADD SP, SP, #<imm>1
Form address from SPADD Rd, SP, #<imm>1
Form address from PCADR Rd, <label>1
SubtractLo and LoSUBS Rd, Rn, Rm1
3-bit immediateSUBS Rd, Rn, #<imm>1
8-bit immediateSUBS Rd, Rd, #<imm>1
With carrySBCS Rd, Rd, Rm1
Immediate from SPSUB SP, SP, #<imm>1
NegateRSBS Rd, Rn, #01
MultiplyMultiplyMULS Rd, Rm, Rd1 or 32[a]
CompareCompareCMP Rn, Rm1
NegativeCMN Rn, Rm1
ImmediateCMP Rn, #<imm>1
LogicalANDANDS Rd, Rd, Rm1
Exclusive OREORS Rd, Rd, Rm1
ORORRS Rd, Rd, Rm1
Bit clearBICS Rd, Rd, Rm1
Move NOTMVNS Rd, Rm1
AND testTST Rn, Rm1
Shift Logical shift left by immediateLSLS Rd, Rm, #<shift>1
Logical shift left by registerLSLS Rd, Rd, Rs1
Logical shift right by immediateLSRS Rd, Rm, #<shift>1
Logical shift right by registerLSRS Rd, Rd, Rs1
Arithmetic shift rightASRS Rd, Rm, #<shift>1
Arithmetic shift right by registerASRS Rd, Rd, Rs1
RotateRotate right by registerRORS Rd, Rd, Rs1
LoadWord, immediate offsetLDR Rd, [Rn, #<imm>]2 or 1[b]
Halfword, immediate offset

LDRH Rd, [Rn, #<imm>]

2 or 1[b]
Byte, immediate offset

LDRB Rd, [Rn, #<imm>]

2 or 1[b]
Word, register offsetLDR Rd, [Rn, Rm]2 or 1[b]
Halfword, register offsetLDRH Rd, [Rn, Rm]2 or 1[b]
Signed halfword, register offsetLDRSH Rd, [Rn, Rm]2 or 1[b]
Byte, register offsetLDRB Rd, [Rn, Rm]2 or 1[b]
Signed byte, register offsetLDRSB Rd, [Rn, Rm]2 or 1[b]
PC-relativeLDR Rd, <label>2 or 1[b]
SP-relativeLDR Rd, [SP, #<imm>]2 or 1[b]
Multiple, excluding baseLDM Rn!, {<loreglist>}1+N[c]
Multiple, including baseLDM Rn, {<loreglist>}1+N[c]
StoreWord, immediate offsetSTR Rd, [Rn, #<imm>]2 or 1[b]
Halfword, immediate offsetSTRH Rd, [Rn, #<imm>]2 or 1[b]
Byte, immediate offsetSTRB Rd, [Rn, #<imm>]2 or 1[b]
Word, register offsetSTR Rd, [Rn, Rm]2 or 1[b]
Halfword, register offsetSTRH Rd, [Rn, Rm]2 or 1[b]
Byte, register offsetSTRB Rd, [Rn, Rm]2 or 1[b]
SP-relativeSTR Rd, [SP, #<imm>]2 or 1[b]
MultipleSTM Rn!, {<loreglist>}1+N[c]
PushPushPUSH {<loreglist>}1+N[c]
Push with link registerPUSH {<loreglist>, LR}1+N[d]
PopPopPOP {<loreglist>}1+N[c]
Pop and returnPOP {<loreglist>, PC}3+N[d]
BranchConditionalB<cc> <label>1 or 2[e]
UnconditionalB <label>2
With linkBL <label>3
With exchangeBX Rm2
With link and exchangeBLX Rm2
ExtendSigned halfword to wordSXTH Rd, Rm1
Signed byte to wordSXTB Rd, Rm1
Unsigned halfwordUXTH Rd, Rm1
Unsigned byteUXTB Rd, Rm1
ReverseBytes in wordREV Rd, Rm1
Bytes in both halfwordsREV16 Rd, Rm1
Signed bottom half wordREVSH Rd, Rm1
State changeSupervisor CallSVC #<imm>- [f]
Disable interruptsCPSID i1
Enable interruptsCPSIE i1
Read special registerMRS Rd, <specreg>3
Write special registerMSR <specreg>, Rn3
BreakpointBKPT #<imm>- [f]
HintSend eventSEV1
Wait for eventWFE2[g]
Wait for interruptWFI2[g]
No operationNOP1
BarriersInstruction synchronizationISB3
Data memoryDMB3
Data synchronizationDSB3

[a] Depends on multiplier implementation.

[b] 2 if to AHB interface or SCS, 1 if to single-cycle I/O port.

[c] N is the number of elements in the list.

[d] N is the number of elements in the list including PC or LR.

[e] 2 if taken, 1 if not-taken.

[f] Cycle count depends on processor and debug configuration.

[g] Excludes time spent waiting for an interrupt or event.

[h] Executes as NOP.

See the ARMv6-M Architecture Reference Manual for more information about the ARMv6-M Thumb instructions.

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