3.5. Processor core registers summary

Table 3.3 shows the processor core register set summary. Each of these registers is 32 bits wide.

Table 3.3. Processor core register set summary

R0-R12R0-R12 are general-purpose registers for data operations.
MSP (R13)

The Stack Pointer (SP) is register R13. In Thread mode, the CONTROLregister indicates the stack pointer to use, Main Stack Pointer (MSP) or Process Stack Pointer (PSP).

PSP (R13)
LR (R14)The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions.
PC (R15)The Program Counter (PC) is register R15. It contains the current program address.

The Program Status Register (PSR) combines:

  • Application Program Status Register (APSR).

  • Interrupt Program Status Register (IPSR).

  • Execution Program Status Register (EPSR).

These registers provide different views of the PSR.


The PRIMASK register prevents activation of all exceptions with configurable priority. For information about the exception model the processor supports, see Exceptions.


The CONTROL register controls the stack used, and optionally the code privilege level, when the processor is in Thread mode.


See the ARMv6-M Architecture Reference Manual for information about the processor core registers and their addresses, access types, and reset values.

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