3.4. Memory model

The processor contains a bus matrix that arbitrates the processor core and optional Debug Access Port (DAP) memory accesses to both the external memory system and to the internal NVIC and debug components.Priority is always given to the processor to ensure that any debug accesses are as non-intrusive as possible. For a zero wait-state system, all debug accesses to system memory, NVIC, and debug resources are completely non-intrusive for typical code execution.The system memory map is ARMv6-M architecture compliant, and is common both to the debugger and processor accesses. Transactions are routed as follows:

The processor supports only word size accesses in the range 0xE0000000 - 0xEFFFFFFF.

Table 3.2 shows the code, data, and device suitability for each region of the default memory map. This is the memory map used by implementations without the optional Memory Protection Unit (MPU), or when an included MPU is disabled. The attributes and permissions of all regions, except that targeting the Cortex-M0+ NVIC and debug components, can be modified using an implemented MPU.

Table 3.2. Default memory map usage

Address rangeCodeDataDevice
0xF0000000 - 0xFFFFFFFF No No Yes
0xE0000000 - 0xEFFFFFFFNoNoNo[a]
0xA0000000 - 0xDFFFFFFFNoNoYes
0x60000000 - 0x9FFFFFFFYesYesNo
0x40000000 - 0x5FFFFFFFNoNoYes
0x20000000 - 0x3FFFFFFFYes[b]YesNo
0x00000000 - 0x1FFFFFFFYesYesNo

[a] Space reserved for Cortex-M0+ NVIC and debug components.

[b] Cortex-M1 devices implementing data Tightly-Coupled Memories (TCMs) in this region do not support code execution from the data TCM.


Note

Regions not marked as suitable for code behave as eXecute-Never (XN) and generate a HardFault exception if code attempts to execute from this location.

See the ARMv6-M Architecture Reference Manual for more information about the memory model.

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