2.1. About the functions

The Cortex-M0+ processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug, single-cycle I/O interfacing, and memory-protection functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile processors.

Figure 2.1 shows the functional blocks of the processor.

Figure 2.1. Functional block diagram

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The implemented device provides:

A low gate count processor that features:
  • The ARMv6-M Thumb® instruction set.

  • Thumb-2 technology.

  • Optionally, an ARMv6-M compliant 24-bit SysTick timer.

  • A 32-bit hardware multiplier. This can be the standard single-cycle multiplier, or a 32-cycle multiplier that has a lower area and performance implementation.

  • Support for either little-endian or byte invariant big-endian data accesses.

  • The ability to have deterministic, fixed-latency, interrupt handling.

  • Load/store multiple and multicycle multiply instructions that can be abandoned and restarted to facilitate rapid interrupt handling.

  • Optionally, Unprivileged/Privileged support for improved system integrity.

  • C Application Binary Interface compliant exception model.

    This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers.

  • Low power sleep-mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return from interrupt sleep-on-exit feature.

NVIC that features:
  • Up to 32 external interrupt inputs, each with four levels of priority.

  • Dedicated Non-Maskable Interrupt (NMI) input.

  • Support for both level-sensitive and pulse-sensitive interrupt lines.

  • Optional Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support.

  • Optional relocation of the vector table.

Optional debug support:
  • Zero to four hardware breakpoints.

  • Zero to two watchpoints.

  • Program Counter Sampling Register (PCSR) for non-intrusive code profiling, if at least one hardware data watchpoint is implemented.

  • Single step and vector catch capabilities.

  • Support for unlimited software breakpoints using BKPT instruction.

  • Non-intrusive access to core peripherals and zero-waitstate system slaves through a compact bus matrix. A debugger can access these devices, including memory, even when the processor is running.

  • Full access to core registers when the processor is halted.

  • Optional, low gate-count CoreSight compliant debug access through a Debug Access Port (DAP) supporting either Serial Wire or JTAG debug connections.

Bus interfaces:
  • Single 32-bit AMBA-3 AHB-Lite system interface that provides simple. integration to all system peripherals and memory.

  • Optional single 32-bit single-cycle I/O port.

  • Optional single 32-bit slave port that supports the DAP.

Optional Memory Protection Unit (MPU):
  • Eight user configurable memory regions.

  • Eight sub-region disables per region.

  • Execute never (XN) support.

  • Default memory map support.

Copyright © 2012 ARM. All rights reserved.ARM DDI 0484C