1.4. Configurable options

Table 1.1 shows the processor configurable options available at implementation time.

Table 1.1. Processor configurable options

FeatureConfigurable option

External interrupts 0-32

Data endiannessLittle-endian or big-endian

SysTick timer

Present or absent
Number of watchpoint comparators[a]0, 1, 2
Number of breakpoint comparators[a]0, 1, 2, 3, 4

Halting debug support

Present or absent

MultiplierFast or small
Single-cycle I/O portPresent or absent
Wake-up interrupt controllerSupported or not supported
Vector Table Offset RegisterPresent or absent
Unprivileged/Privileged supportPresent or absent
Memory Protection UnitNot present or 8-region
Reset all registersPresent or absent
Instruction fetch width16-bit only or mostly 32-bit

[a] Only when halting debug support is present.

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