4.2. System control register summary

Table 4.1 gives the system control registers. Each of these registers is 32 bits wide.

Table 4.1. System control registers

NameDescription
SYST_CSRSysTick Control and Status Register in the ARMv6-M Architecture Reference Manual.
SYST_RVRSysTick Reload Value Register in the ARMv6-M Architecture Reference Manual.
SYST_CVRSysTick Current Value Register in the ARMv6-M Architecture Reference Manual.
SYST_CALIB[a]SysTick Calibration value Register in the ARMv6-M Architecture Reference Manual.
CPUIDSee CPUID Register.
ICSRInterrupt Control State Register in the ARMv6-M Architecture Reference Manual.
AIRCR[a] Application Interrupt and Reset Control Register in the ARMv6-M Architecture Reference Manual.
CCR Configuration and Control Register in the ARMv6-M Architecture Reference Manual.
SHPR2System Handler Priority Register 2 in the ARMv6-M Architecture Reference Manual.
SHPR3System Handler Priority Register 3 in the ARMv6-M Architecture Reference Manual.
SHCSR System Handler Control and State Register in the ARMv6-M Architecture Reference Manual.
VTOR[b]Vector table Offset Register in the ARMv6-M Architecture Reference Manual.
ACTLR[c]Auxiliary Control Register in the ARMv6-M Architecture Reference Manual.

[a] This value is configured by the implementer during implementation. See the documentation supplied by your implementer for more information.

[b] If implemented, the VTOR enables bits[31:8] of the vector table address to be specified.

[c] Implemented as RAZ/WI


Note

  • All system control registers are only accessible using word transfers. Any attempt to read or write a halfword or byte is Unpredictable.

  • If the processor is implemented without the SysTick timer, the SYST_CSR, SYST_RVR, SYST_CVR, and SYST_CALIB registers are RAZ/WI.

  • See the ARMv6-M Architecture Reference Manual for more information about the system control registers, and their addresses and access types, and reset values not shown in Table 4.1.

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