CoreSight™ MTB-M0+ Technical Reference Manual

Revision: r0p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the CoreSight MTB-M0+
1.2. Compliance
1.2.1. Advanced Microcontroller Bus Architecture
1.2.2. Debug authentication interface
1.3. Features
1.4. Interfaces
1.4.1. AHB-Lite slave interface
1.4.2. Processor execution trace interface
1.4.3. Synchronous SRAM master interface
1.5. Configurable options
1.6. Test features
1.7. Product documentation and design flow
1.7.1. Documentation
1.7.2. Design flow
1.8. Product revisions
2. Functional description
2.1. About the functions
2.2. Interfaces
2.2.1. Clock and reset interface
2.2.2. AHB-Lite interface
2.2.3. Execution trace interface
2.2.4. External trace enable interface
2.2.5. SRAM interface
2.2.6. Debug authentication interface
2.3. Operation
2.3.1. MTB execution trace packet format
2.3.2. Trace start and stop
3. Programmers model
3.1. About the programmers model
3.2. Memory model
3.3. Register summary
3.3.1. Trace control registers
3.3.2. CoreSight registers
3.4. Register descriptions
3.4.1. POSITION Register
3.4.2. MASTER Register
3.4.3. FLOW Register
3.4.4. BASE Register
A. Signal descriptions
A.1. About the signal descriptions
A.2. Clock, reset, and control signals
A.3. AMBA AHB-Lite interface
A.4. SRAM memory interface
A.5. Execution trace interface
A.6. External trace control interface
A.7. Debug authentication interface
A.8. Miscellaneous signals
B. Example Programming Sequences
B.1. Discovery
B.2. Trace Enable Programming Sequence
B.3. Trace Disable Programming Sequence
C. Revisions

Proprietary Notice

Words and logos marked with® or ™ are registered trademarks or trademarks of ARM® in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A19 January 2012First release for r0p0
Revision B14 December 2012First release for r0p1
Copyright © 2012 ARM. All rights reserved.ARM DDI 0486B
Non-ConfidentialID011213