ARM® Cortex®-A57 MPCore™ Processor Technical Reference Manual

Revision: r1p0

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1. Introduction
1.1. About the Cortex-A57 MPCore processor
1.2. Compliance
1.2.1. ARM architecture
1.2.2. Advanced Microcontroller Bus Architecture (AMBA)
1.2.3. CHI architecture
1.2.4. Generic Interrupt Controller architecture
1.2.5. Generic Timer architecture
1.2.6. Debug architecture
1.2.7. Embedded Trace Macrocell architecture
1.3. Features
1.4. Interfaces
1.5. Implementation options
1.6. Test features
1.7. Product documentation and design flow
1.7.1. Documentation
1.7.2. Design flow
1.8. Product revisions
2. Functional Description
2.1. About the Cortex-A57 MPCore multiprocessor functions
2.1.1. Components of the multiprocessor
2.2. Interfaces
2.2.1. Memory interface
2.2.2. Accelerator Coherency Port
2.2.3. GIC CPU interface
2.2.4. Debug interface
2.2.5. Trace interface
2.2.6. PMU interface
2.2.7. Generic Timer interface
2.2.8. Cross trigger interface
2.2.9. Power management interface
2.2.10. DFT
2.2.11. MBIST
2.3. Clocking and resets
2.3.1. Clocks
2.3.2. Resets
2.4. Power management
2.4.1. Dynamic power management
2.4.2. Power domains
2.4.3. Power modes
2.4.4. Using SMPEN as a power mode indicator
3. Programmers Model
3.1. About the programmers model
3.2. ARMv8 architecture concepts
3.2.1. Execution state
3.2.2. Exception levels
3.2.3. Security state
3.2.4. Rules for changing Exception state
3.2.5. Stack Pointer selection
3.2.6. ARMv8 security model
3.2.7. Instruction set state
3.2.8. AArch32 execution modes
3.3. ThumbEE instruction set
3.4. Jazelle implementation
3.4.1. Register summary
3.4.2. Register description
3.5. Memory model
4. System Control
4.1. About system control
4.1.1. Registers affected by CP15SDISABLE
4.2. AArch64 register summary
4.2.1. AArch64 identification registers
4.2.2. AArch64 exception handling registers
4.2.3. AArch64 virtual memory control registers
4.2.4. AArch64 other System registers
4.2.5. AArch64 cache maintenance operations
4.2.6. AArch64 TLB maintenance operations
4.2.7. AArch64 address translation operations
4.2.8. AArch64 miscellaneous operations
4.2.9. AArch64 Performance Monitors registers
4.2.10. AArch64 reset registers
4.2.11. Security registers
4.2.12. AArch64 virtualization registers
4.2.13. AArch64 EL2 TLB maintenance operations
4.2.14. Generic Timer registers
4.2.15. AArch64 implementation defined registers
4.3. AArch64 register descriptions
4.3.1. Main ID Register, EL1
4.3.2. Multiprocessor Affinity Register, EL1
4.3.3. Revision ID Register, EL1
4.3.4. AArch32 Processor Feature Register 0, EL1
4.3.5. AArch32 Processor Feature Register 1, EL1
4.3.6. AArch32 Debug Feature Register 0, EL1
4.3.7. AArch32 Auxiliary Feature Register 0, EL1
4.3.8. AArch32 Memory Model Feature Register 0, EL1
4.3.9. AArch32 Memory Model Feature Register 1, EL1
4.3.10. AArch32 Memory Model Feature Register 2, EL1
4.3.11. AArch32 Memory Model Feature Register 3, EL1
4.3.12. AArch32 Instruction Set Attribute Register 0, EL1
4.3.13. AArch32 Instruction Set Attribute Register 1, EL1
4.3.14. AArch32 Instruction Set Attribute Register 2, EL1
4.3.15. AArch32 Instruction Set Attribute Register 3, EL1
4.3.16. AArch32 Instruction Set Attribute Register 4, EL1
4.3.17. AArch32 Instruction Set Attribute Register 5, EL1
4.3.18. AArch64 Processor Feature Register 0, EL1
4.3.19. AArch64 Debug Feature Register 0, EL1
4.3.20. AArch64 Instruction Set Attribute Register 0, EL1
4.3.21. AArch64 Memory Model Feature Register 0, EL1
4.3.22. Cache Size ID Register, EL1
4.3.23. Cache Level ID Register, EL1
4.3.24. Auxiliary ID Register, EL1
4.3.25. Cache Size Selection Register, EL1
4.3.26. Cache Type Register, EL0
4.3.27. Data Cache Zero ID, EL0
4.3.28. Virtualization Processor ID Register, EL2
4.3.29. Virtualization Multiprocessor ID Register, EL2
4.3.30. System Control Register, EL1
4.3.31. Auxiliary Control Register, EL1
4.3.32. Architectural Feature Access Control Register, EL1
4.3.33. Auxiliary Control Register, EL2
4.3.34. Hypervisor Configuration Register, EL2
4.3.35. Architectural Feature Trap Register, EL2
4.3.36. Hypervisor System Trap Register
4.3.37. Hyp Auxiliary Configuration Register
4.3.38. System Control Register, EL3
4.3.39. Auxiliary Control Register, EL3
4.3.40. Architectural Feature Trap Register, EL3
4.3.41. Translation Control Register, EL1
4.3.42. Translation Control Register, EL2
4.3.43. Virtualization Translation Control Register, EL2
4.3.44. Translation Table Base Register 0, EL1
4.3.45. Translation Table Base Register 0, EL3
4.3.46. Translation Table Base Register 1, EL1
4.3.47. Translation Control Register, EL3
4.3.48. Auxiliary Fault Status Register 0, EL1 and EL3
4.3.49. Auxiliary Fault Status Register 1, EL1 and EL3
4.3.50. Exception Syndrome Register, EL1 and EL3
4.3.51. Instruction Fault Status Register, EL2
4.3.52. Auxiliary Fault Status Register 0, EL2 and Hyp Auxiliary Data Fault Status Register
4.3.53. Auxiliary Fault Status Register 1, EL2 and Hyp Auxiliary Instruction Fault Status Register
4.3.54. Exception Syndrome Register, EL2
4.3.55. Physical Address Register, EL1
4.3.56. Auxiliary Memory Attribute Indirection Register, EL1 and EL3
4.3.57. Auxiliary Memory Attribute Indirection Register, EL2
4.3.58. L2 Control Register, EL1
4.3.59. L2 Extended Control Register, EL1
4.3.60. Reset Vector Base Address, EL3
4.3.61. Reset Management Register, EL3
4.3.62. Instruction L1 Data n Register, EL1
4.3.63. Data L1 Data n Register, EL1
4.3.64. RAM Index operation
4.3.65. L2 Auxiliary Control Register, EL1
4.3.66. CPU Auxiliary Control Register, EL1
4.3.67. CPU Extended Control Register, EL1
4.3.68. CPU Memory Error Syndrome Register, EL1
4.3.69. L2 Memory Error Syndrome Register, EL1
4.3.70. Configuration Base Address Register, EL1
4.4. AArch32 register summary
4.4.1. c0 registers
4.4.2. c1 registers
4.4.3. c2 registers
4.4.4. c3 registers
4.4.5. c5 registers
4.4.6. c6 registers
4.4.7. c7 register
4.4.8. c7 System operations
4.4.9. c8 System operations
4.4.10. c9 registers
4.4.11. c10 registers
4.4.12. c12 registers
4.4.13. c13 registers
4.4.14. c14 registers
4.4.15. c15 registers
4.4.16. 64-bit registers
4.4.17. Identification registers
4.4.18. CPUID registers
4.4.19. Virtual memory control registers
4.4.20. Fault and Exception handling registers
4.4.21. Other System registers
4.4.22. Cache maintenance operations
4.4.23. TLB maintenance operations
4.4.24. Address translation operations
4.4.25. Miscellaneous operations
4.4.26. Performance Monitors registers
4.4.27. Security registers
4.4.28. Virtualization registers
4.4.29. Hyp mode TLB maintenance operations
4.4.30. Generic Timer registers
4.4.31. Implementation defined registers
4.5. AArch32 register descriptions
4.5.1. TCM Type Register
4.5.2. TLB Type Register
4.5.3. Multiprocessor Affinity Register
4.5.4. Virtualization Multiprocessor ID Register
4.5.5. System Control Register
4.5.6. Architectural Feature Access Control Register
4.5.7. Secure Configuration Register
4.5.8. Non-secure Access Control Register
4.5.9. Secure Debug Configuration Register
4.5.10. Hyp Configuration Register
4.5.11. Hyp Configuration Register 2
4.5.12. Hyp Debug Control Register
4.5.13. Hyp Architectural Feature Trap Register
4.5.14. Translation Table Base Register 0 and Register 1
4.5.15. Translation Table Base Control Register
4.5.16. Hyp Translation Control Register
4.5.17. Data Fault Status Register
4.5.18. Physical Address Register
4.5.19. Primary Region Remap Register
4.5.20. Memory Attribute Indirection Register 0
4.5.21. Normal Memory Remap Register.
4.5.22. Memory Attribute Indirection Register 1
4.5.23. FCSE Process ID Register
4.5.24. Configuration Base Address Register
5. Memory Management Unit
5.1. About the MMU
5.2. TLB organization
5.2.1. L1 instruction TLB
5.2.2. L1 data TLB
5.2.3. L2 TLB
5.3. TLB match process
5.4. Memory access sequence
5.5. MMU enabling and disabling
5.6. Intermediate table walk caches
5.7. External aborts
5.7.1. External aborts on data read or write
5.7.2. Synchronous and asynchronous aborts
6. Level 1 Memory System
6.1. About the L1 memory system
6.2. Cache organization
6.3. L1 instruction memory system
6.3.1. Instruction cache disabled behavior
6.3.2. Instruction cache speculative memory accesses
6.3.3. Fill buffers
6.3.4. Non-cacheable fetching
6.3.5. Parity error handling
6.3.6. Hardware L1 I-cache prefetching
6.4. L1 data memory system
6.4.1. Behavior for different memory types
6.4.2. Coherence
6.4.3. Cache disabled behavior
6.4.4. Non-cacheable streaming enhancement
6.4.5. Synchronization primitives
6.4.6. Load/Store unprivileged instructions
6.4.7. Preload instruction behavior
6.4.8. Error Correction Code
6.5. Program flow prediction
6.5.1. Predicted and non-predicted instructions
6.5.2. Return stack predictions
6.5.3. Indirect predictor
6.5.4. Static predictor
6.5.5. Enabling program flow prediction
6.5.6. BTB invalidation and context switches
6.6. L1 RAM memories
7. Level 2 Memory System
7.1. About the L2 memory system
7.2. Cache organization
7.2.1. L2 cache bank structure
7.2.2. Strictly-enforced inclusion property with L1 data caches
7.2.3. Enabling and disabling the L2 cache
7.2.4. Error correction code
7.2.5. Register slice support for large cache sizes
7.3. L2 RAM memories
7.4. L2 cache prefetcher
7.5. Cache coherency
7.6. Asynchronous errors
7.7. External coherent interfaces
7.7.1. L2 memory interface attributes
7.7.2. Interface modes
7.7.3. Snoop filter support
7.7.4. Distributed virtual memory transactions
7.7.5. External memory attributes
7.7.6. ACE ARID and AWID assignment
7.7.7. CHI LPID assignment
7.7.8. ACE supported transfers
7.7.9. CHI link layer flow control
7.7.10. CHI DVM acceptance capability
7.7.11. L2 Auxiliary Control Register settings
7.8. ACP
7.8.1. Transfer size support
7.8.2. ACP ARUSER and AWUSER signals
8. Generic Interrupt Controller CPU Interface
8.1. About the GIC
8.2. GIC functional description
8.2.1. GIC memory map
8.2.2. Interrupt sources
8.2.3. Interrupt priority levels
8.2.4. GIC bypass modes
8.2.5. nIRQ and nVFIQ inputs
8.3. GIC programmers model
8.3.1. CPU interface register summary
8.3.2. CPU interface memory-mapped register descriptions
8.3.3. CPU interface System register descriptions
8.3.4. Virtual interface control register summary
8.3.5. Virtual interface control register descriptions
8.3.6. Virtual CPU interface register summary
8.3.7. Virtual CPU interface register descriptions
9. Generic Timer
9.1. About the Generic Timer
9.2. Generic Timer functional description
9.3. Generic Timer register summary
9.3.1. AArch64 Generic Timer register summary
9.3.2. AArch32 Generic Timer register summary
10. Debug
10.1. About debug
10.1.1. Debug host
10.1.2. Protocol converter
10.1.3. Debug target
10.1.4. The debug unit
10.1.5. Self-hosted debug
10.2. Debug register interfaces
10.2.1. Processor interfaces
10.2.2. Breakpoints and watchpoints
10.2.3. Effects of resets on debug registers
10.2.4. External access permissions
10.3. AArch64 debug register summary
10.4. AArch64 debug register descriptions
10.4.1. Debug Breakpoint Control Registers, EL1
10.4.2. Debug Watchpoint Control Registers, EL1
10.5. AArch32 debug register summary
10.6. AArch32 debug register descriptions
10.6.1. Debug ID Register
10.6.2. Debug Device ID Register 1
10.6.3. Debug Device ID Register
10.7. Memory-mapped register summary
10.8. Memory-mapped register descriptions
10.8.1. External Debug Reserve Control Register
10.8.2. External Debug Auxiliary Control Register
10.8.3. External Debug Integration Output Control Register
10.8.4. External Debug Integration Input Status Register
10.8.5. External Debug Integration Mode Control Register
10.8.6. External Debug Device ID Register 1
10.8.7. External Debug Device ID Register 0
10.8.8. Debug Peripheral Identification Registers
10.8.9. Debug Component Identification Registers
10.9. Debug events
10.9.1. Watchpoint debug events
10.9.2. Debug OS Lock
10.10. External debug interface
10.10.1. Debug memory map
10.10.2. DBGPWRDUP debug signal
10.10.3. DBGL1RSTDISABLE debug signal
10.10.4. Changing the authentication signals
10.11. ROM table
10.11.1. ROM table register interface
10.11.2. ROM table register summary
10.11.3. ROM table register descriptions
10.11.4. ROM table Debug Peripheral Identification Registers
10.11.5. ROM table Debug Component Identification Registers
11. Performance Monitor Unit
11.1. About the PMU
11.2. PMU functional description
11.2.1. Event interface
11.2.2. System register and APB interface
11.2.3. Counters
11.2.4. PMU register interfaces
11.2.5. External register access permissions
11.3. AArch64 PMU register summary
11.4. AArch64 PMU register descriptions
11.4.1. Performance Monitors Control Register, EL0
11.4.2. Performance Monitors Common Event Identification Register 0, EL0
11.5. AArch32 PMU register summary
11.6. Memory-mapped register summary
11.7. Memory-mapped register descriptions
11.7.1. Performance Monitors Control Register, EL0
11.7.2. Performance Monitors Program Counter Sample Register
11.7.3. Performance Monitors Context ID Sample Register
11.7.4. Performance Monitors Virtual Context Sample Register
11.7.5. Performance Monitors Snapshot Status Register
11.7.6. Performance Monitors Overflow Status Snapshot Register
11.7.7. Performance Monitors Cycle Counter Snapshot Register
11.7.8. Performance Monitors Event Counters Snapshot Registers
11.7.9. Performance Monitors Snapshot Control Register
11.7.10. Performance Monitors Snapshot Reset Register
11.7.11. Performance Monitors Configuration Register
11.7.12. PMU Peripheral Identification Registers
11.7.13. PMU Component Identification Registers
11.8. Events
11.9. Interrupts
11.10. Exporting PMU events
11.10.1. External hardware
11.10.2. Debug trace hardware
12. Cross Trigger
12.1. About the cross trigger
12.2. Trigger inputs and outputs
12.3. CTI
12.4. CTM
12.5. Cross trigger register summary
12.5.1. External register access permissions
12.6. Cross trigger register descriptions
12.6.1. CTI Device Identification register
12.6.2. CTI Integration Mode Control register
12.6.3. CTI Integration Test Channel In Acknowledge register
12.6.4. CTI Integration Test Trigger In Acknowledge register
12.6.5. CTI Integration Test Channel Out register
12.6.6. CTI Integration Test Trigger Out register
12.6.7. CTI Integration Test Channel Out Acknowledge register
12.6.8. CTI Integration Test Trigger Out Acknowledge register
12.6.9. CTI Integration Test Channel In register
12.6.10. CTI Integration Test Trigger In register
12.6.11. CTI Peripheral Identification Registers
12.6.12. CTI Component Identification Registers
13. Embedded Trace Macrocell
13.1. About ETM
13.2. ETM trace generation options and resources
13.3. ETM functional description
13.4. Reset
13.5. ETM register interfaces
13.5.1. Access permissions
13.6. Register summary
13.7. Register descriptions
13.7.1. Trace Configuration Register
13.7.2. Trace Auxiliary Control Register
13.7.3. Trace Event Control 0 Register
13.7.4. Trace Event Control 1 Register
13.7.5. Trace Synchronization Period Register
13.7.6. Trace Cycle Count Control Register
13.7.7. Trace ID Register
13.7.8. ViewInst Main Control Register
13.7.9. External Input Select Register
13.7.10. ID Register 8
13.7.11. ID Register 9
13.7.12. ID Register 10
13.7.13. ID Register 11
13.7.14. ID Register 12
13.7.15. ID Register 13
13.7.16. Implementation Defined Register 0
13.7.17. Trace ID Register 0
13.7.18. Trace ID Register 1
13.7.19. Trace ID Register 2
13.7.20. Trace ID Register 3
13.7.21. Trace ID Register 4
13.7.22. Trace ID Register 5
13.7.23. Resource Selection Control Registers
13.7.24. Address Comparator Access Type Registers
13.7.25. Context ID Comparator Value Register 0
13.7.26. VMID Comparator Value Register 0
13.7.27. Context ID Comparator Control Register 0
13.7.28. Trace Integration Miscellaneous Outputs Register
13.7.29. Trace Integration Miscellaneous Input Register
13.7.30. Trace Integration Test ATB Data Register 0
13.7.31. Trace Integration Test ATB Control Register 2
13.7.32. Trace Integration Test ATB Control Register 1
13.7.33. Trace Integration Test ATB Control Register 0
13.7.34. Trace Integration Mode Control register
13.7.35. Trace Device Affinity register 0
13.7.36. Trace Device Affinity register 1
13.7.37. ETM Peripheral Identification Registers
13.7.38. ETM Component Identification Registers
13.8. Interaction with debug and the Performance Monitor Unit
13.8.1. Interaction with the Performance Monitor Unit
13.8.2. Effect of debug double lock on trace register access
14. Advanced SIMD and Floating-point
14.1. About Advanced SIMD and Floating-point
14.1.1. Advanced SIMD support
14.1.2. Floating-point support
14.2. Programmers model for Advanced SIMD and Floating-point
14.3. AArch64 register summary
14.4. AArch64 register descriptions
14.4.1. Floating-point Control Register
14.4.2. Floating-point Status Register
14.4.3. Media and VFP Feature Register 0, EL1
14.4.4. Media and VFP Feature Register 1, EL1
14.4.5. Media and VFP Feature Register 2, EL1
14.4.6. Floating-point Exception Control Register 32, EL2
14.5. AArch32 register summary
14.6. AArch32 register descriptions
14.6.1. Floating-point System ID Register
14.6.2. Floating-point Status and Control Register
A. Signal Descriptions
A.1. About the signal descriptions
A.2. Clock signals
A.3. Reset signals
A.4. Configuration signals
A.5. GIC CPU interface signals
A.6. Generic Timer signals
A.7. Power control signals
A.8. ACE and CHI interface signals
A.8.1. Configuration signals
A.8.2. Asynchronous error signals
A.9. CHI interface signals
A.9.1. CHI clock and configuration signals
A.9.2. Transmit request virtual channel signals
A.9.3. Transmit response virtual channel signals
A.9.4. Transmit data virtual channel signals
A.9.5. Receive snoop virtual channel signals
A.9.6. Receive response virtual channel signals
A.9.7. Receive data virtual channel signals
A.9.8. System address map signals
A.10. ACE interface signals
A.10.1. Clock and configuration signals
A.10.2. Write address channel signals
A.10.3. Write data channel signals
A.10.4. Write response channel signals
A.10.5. Read address channel signals
A.10.6. Read data channel signals
A.10.7. Snoop address channel signals
A.10.8. Snoop response channel signals
A.10.9. Snoop data channel handshake signals
A.10.10. Read/Write acknowledge signals
A.11. ACP interface signals
A.11.1. Clock and configuration signals
A.11.2. Write address channel signals
A.11.3. Write data channel signals
A.11.4. Write response channel signals
A.11.5. Read address channel signals
A.11.6. Read data channel signals
A.12. Debug interface signals
A.12.1. APB interface signals
A.12.2. Authentication interface signals
A.12.3. Miscellaneous debug signals
A.13. ETM interface
A.13.1. ATB interface
A.13.2. Miscellaneous ETM signal
A.14. Cross trigger channel interface
A.15. PMU signals
A.16. DFT and MBIST signals
A.16.1. DFT signals
A.16.2. MBIST interface
B. AArch32 UNPREDICTABLE Behaviors
B.1. UNPREDICTABLE behaviors
B.1.1. Use of R15 by instruction
B.1.2. Load or store accesses that span a page boundary
B.2. Debug UNPREDICTABLE behaviors
B.2.1. A32 BKPT instruction with condition code not AL
B.2.2. Address match breakpoint match only on second halfword of an instruction
B.2.3. Address matching breakpoint on A32 instruction with DBGBCRn.BAS=1100
B.2.4. Address match breakpoint match on T32 instruction at DBGBCRn+2 with DBGBCRn.BAS=1111
B.2.5. Address mismatch breakpoint match only on second halfword of an instruction
B.2.6. Address mismatch breakpoint match on T32 instruction at DBGBCRn+2 with DBGBCRn.BAS=1111
B.2.7. Other mismatch breakpoint matches any address in current mode and state
B.2.8. Mismatch breakpoint on branch to self
B.2.9. Link to nonexistent breakpoint or breakpoint that is not context-aware
B.2.10. DBGWCRn_EL1.MASK!=00000 and DBGWCRn_EL1.BAS!=11111111
B.2.11. Address-matching Vector catch on 32-bit T32 instruction at vector–2
B.2.12. Address-matching Vector catch on 32-bit T32 instruction at vector+2
B.2.13. Address-matching Vector catch and Breakpoint on same instruction
B.2.14. Address match breakpoint with DBGBCRn_EL1.BAS=0000
B.2.15. DBGWCRn_EL1.BAS specifies a non-contiguous set of bytes within a doubleword
B.2.16. A32 HLT instruction with condition code not AL
B.2.17. Execute instruction at a given EL when the corresponding EDECCR bit is 1 and Halting is allowed
B.2.18. Unlinked Context matching and Address mismatch breakpoints taken to Abort mode
B.2.19. Vector catch on Data or Prefetch Abort, and taken to Abort mode
B.2.20. H > N or H = 0 at Non-secure EL1 and EL0, including value read from PMCR_EL0.N
B.2.21. H > N or H = 0: value read back in MDCR_EL2.HPMN
B.2.22. P ≥ M and P ≠ 31: reads and writes of PMXEVTYPER_EL0 and PMXEVCNTR_EL0
B.2.23. P ≥ M and P ≠ 31: value read in PMSELR_EL0.SEL
B.2.24. P = 31: reads and writes of PMXEVCNTR_EL0
B.2.25. n ≥ M: Direct access to PMEVCNTRn_EL0 and PMEVTYPERn_EL0
B.2.26. Exiting Debug state while instruction issued through EDITR is in flight
B.2.27. Using memory-access mode with a non-word-aligned address
B.2.28. Access to memory-mapped registers mapped to Normal memory
B.2.29. Not word-sized accesses or (AArch64 only) doubleword-sized accesses
B.2.30. External debug write to register that is being reset
B.2.31. Accessing reserved debug registers
B.2.32. Clearing the clear-after-read EDPRSR bits when Core power domain is on, and DoubleLockStatus() is TRUE
C. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. Example multiprocessor configuration
2.1. Block diagram
2.2. ACLKENM with CLK:ACLKM ratio changing from 3:1 to 1:1
2.3. SCLKEN with CLK:SCLK ratio changing from 3:1 to 1:1
2.4. ACLKENS with CLK:ACLKS ratio changing from 3:1 to 1:1
2.5. PCLKENDBG with PCLKDBG:internal PCLKDBG ratio changing from 2:1 to 1:1
2.6. ATCLKEN with CLK:ATCLK ratio at 2:1
2.7. CNTCLKEN with CLK:CNTCLK ratio at 2:1
2.8. Powerup reset timing
2.9. Warm reset timing
2.10. Debug PCLKDBG reset timing
2.11. CLREXMON request and acknowledge handshake
2.12. L2 Wait For Interrupt timing
2.13. L2 hardware cache flush timing
2.14. Successful retention timing
2.15. Denied retention timing
2.16. L2 dynamic retention timing
2.17. Power domains
3.1. ARMv8 security model when EL3 is using AArch64
3.2. ARMv8 security model when EL3 is using AArch32
4.1. MIDR_EL1 bit assignments
4.2. MPIDR_EL1 bit assignments
4.3. REVIDR_EL1 bit assignments
4.4. ID_PFR0_EL1 bit assignments
4.5. ID_PFR1_EL1 bit assignments
4.6. ID_DFR0_EL1 bit assignments
4.7. ID_MMFR0_EL1 bit assignments
4.8. ID_MMFR1_EL1 bit assignments
4.9. ID_MMFR2_EL1 bit assignments
4.10. ID_MMFR3_EL1 bit assignments
4.11. ID_ISAR0_EL1 bit assignments
4.12. ID_ISAR1_EL1 bit assignments
4.13. ID_ISAR2_EL1 bit assignments
4.14. ID_ISAR3_EL1 bit assignments
4.15. ID_ISAR4_EL1 bit assignments
4.16. ID_ISAR5_EL1 bit assignments
4.17. ID_AA64PFR0_EL1 bit assignments
4.18. ID_AA64DFR0_EL1 bit assignments
4.19. ID_AA64ISAR0_EL1 bit assignments
4.20. ID_AA64MMFR0_EL1 bit assignments
4.21. CCSIDR_EL1 bit assignments
4.22. CLIDR_EL1 bit assignments
4.23. CSSELR_EL1 bit assignments
4.24. CTR_EL0 bit assignments
4.25. DCZID_EL0 bit assignments
4.26. VPIDR_EL2 bit assignments
4.27. VMPIDR_EL2 bit assignments
4.28. SCTLR_EL1 bit assignments
4.29. CPACR_EL1 bit assignments
4.30. ACTLR_EL2 bit assignments
4.31. HCR_EL2 bit assignments
4.32. CPTR_EL2 bit assignments
4.33. HSTR_EL2 bit assignments
4.34. SCTLR_EL3 bit assignments
4.35. ACTLR_EL3 bit assignments
4.36. CPTR_EL3 bit assignments
4.37. TCR_EL1 bit assignments
4.38. TCR_EL2 bit assignments
4.39. VTCR_EL2 bit assignments
4.40. TTBR0_EL1 bit assignments
4.41. TTBR0_EL3 bit assignments
4.42. TTBR1_EL1 bit assignments
4.43. TCR_EL3 bit assignments
4.44. ESR_EL1 and ESR_EL3 bit assignments
4.45. IFSR32_EL2 bit assignments for Short-descriptor translation table format
4.46. IFSR32_EL2 bit assignments for Long-descriptor translation table format
4.47. ESR_EL2 bit assignments
4.48. PAR_EL1 pass bit assignments
4.49. PAR_EL1 fail bit assignments
4.50. L2CTRL_EL1 bit assignments
4.51. L2ECTLR_EL1 bit assignments
4.52. RVBAR_EL3 bit assignments
4.53. RMR_EL3 bit assignments
4.54. IL1DATAn_EL1 bit assignments
4.55. DL1DATAn_EL1 bit assignments
4.56. RAMINDEX bit assignments
4.57. RAMINDEX bit assignments for L1-I Tag RAM
4.58. RAMINDEX bit assignments for L1-I Data RAM
4.59. RAMINDEX bit assignments for L1-I BTB RAM
4.60. RAMINDEX bit assignments for L1-I GHB RAM
4.61. RAMINDEX bit assignments for L1-I TLB array
4.62. RAMINDEX bit assignments for L1-I indirect predictor RAM
4.63. RAMINDEX bit assignments for L1-D Tag RAM
4.64. RAMINDEX bit assignments for L1-D Data RAM
4.65. RAMINDEX bit assignments for L1-D TLB array
4.66. RAMINDEX bit assignments for L2 Tag RAM
4.67. RAMINDEX bit assignments for L2 Data RAM
4.68. RAMINDEX bit assignments for L2 Snoop Tag RAM
4.69. RAMINDEX bit assignments for L2 Data ECC RAM
4.70. RAMINDEX bit assignments for L2 Dirty RAM
4.71. RAMINDEX bit assignments for L2 TLB RAM
4.72. L2ACTLR_EL1 bit assignments
4.73. CPUACTLR_EL1[63:32] bit assignments
4.74. CPUACTLR_EL1[31:0] bit assignments
4.75. CPUECTLR_EL1 bit assignments
4.76. CPUMERRSR_EL1 bit assignments
4.77. L2MERRSR_EL1 bit assignments
4.78. CBAR_EL1 bit assignments
4.79. TLBTR bit assignments
4.80. MPIDR bit assignments
4.81. VMPIDR bit assignments
4.82. SCTLR bit assignments
4.83. CPACR bit assignments
4.84. SCR bit assignments
4.85. NSACR bit assignments
4.86. SDCR bit assignments
4.87. HCR bit assignments
4.88. HCR2 bit assignments
4.89. HDCR bit assignments
4.90. HCPTR bit assignments
4.91. DFSR bit assignments for Short-descriptor translation table format
4.92. DFSR bit assignments for Long-descriptor translation table format
4.93. CBAR bit assignments
7.1. L2 cache bank structure
8.1. GICC_IIDR bit assignments
8.2. GICH_VTR bit assignments
8.3. ICH_VTR_EL2 bit assignments
10.1. Typical debug system
10.2. DBGBCRn_EL1 bit assignments
10.3. DBGWCRn_EL1 bit assignments
10.4. DBGDIDR bit assignments
10.5. DBGDEVID1 bit assignments
10.6. DBGDEVID bit assignments
10.7. EDRCR bit assignments
10.8. EDACR bit assignments
10.9. EDITOCTRL bit assignments
10.10. EDITISR bit assignments
10.11. EDITCTRL bit assignments
10.12. EDDEVID1 bit assignments
10.13. EDDEVID bit assignments
10.14. EDPIDR0 bit assignments
10.15. EDPIDR1 bit assignments
10.16. EDPIDR2 bit assignments
10.17. EDPIDR3 bit assignments
10.18. EDPIDR4 bit assignments
10.19. EDCIDR0 bit assignments
10.20. EDCIDR1 bit assignments
10.21. EDCIDR2 bit assignments
10.22. EDCIDR3 bit assignments
10.23. External debug interface, including APBv3 slave port
10.24. ROMENTRY bit assignments
10.25. ROMPIDR0 bit assignments
10.26. ROMPIDR1 bit assignments
10.27. ROMPIDR2 bit assignments
10.28. ROMPIDR3 bit assignments
10.29. ROMPIDR4 bit assignments
10.30. ROMCIDR0 bit assignments
10.31. ROMCIDR1 bit assignments
10.32. ROMCIDR2 bit assignments
10.33. ROMCIDR3 bit assignments
11.1. PMU block diagram
11.2. PMCR_EL0 bit assignments
11.3. PMCEID0_EL0 bit assignments
11.4. PMCR_EL0 bit assignments, memory-mapped view
11.5. PMSSR bit assignments
11.6. PMSCR bit assignments
11.7. PMSRR bit assignments
11.8. PMCFGR bit assignments
11.9. PMPIDR0 bit assignments
11.10. PMPIDR1 bit assignments
11.11. PMPIDR2 bit assignments
11.12. PMPIDR3 bit assignments
11.13. PMPIDR4 bit assignments
11.14. PMCIDR0 bit assignments
11.15. PMCIDR1 bit assignments
11.16. PMCIDR2 bit assignments
11.17. PMCIDR3 bit assignments
12.1. Debug system components
12.2. CTIDEVID bit assignments
12.3. CTIITCTRL bit assignment
12.4. CTIITCHINACK bit assignments
12.5. CTIITTRIGINACK bit assignments
12.6. CTIITCHOUT bit assignments
12.7. CTIITTRIGOUT bit assignments
12.8. CTIITCHOUTACK bit assignments
12.9. CTIITTRIGOUTACK bit assignments
12.10. CTIITCHIN bit assignments
12.11. CTIITTRIGIN bit assignments
12.12. CTIPIDR0 bit assignments
12.13. CTIPIDR1 bit assignments
12.14. CTIPIDR2 bit assignments
12.15. CTIPIDR3 bit assignments
12.16. CTIPIDR4 bit assignments
12.17. CTICIDR0 bit assignments
12.18. CTICIDR1 bit assignments
12.19. CTICIDR2 bit assignments
12.20. CTICIDR3 bit assignments
13.1. ETM functional blocks
13.2. TRCCONFIGR bit assignments
13.3. TRCAUXCTLR bit assignments
13.4. TRCEVENTCL0R bit assignments
13.5. TRCEVENTCL1R bit assignments
13.6. TRCSYNCPR bit assignments
13.7. TRCCCCTLR bit assignments
13.8. TRCTRACEIDR bit assignments
13.9. TRCVICTLR bit assignments
13.10. TRCEXTINSELR bit assignments
13.11. TRCIDR8 bit assignments
13.12. TRCID9 bit assignments
13.13. TRCIDR10 bit assignments
13.14. TRCIDR11 bit assignments
13.15. TRCIDR12 bit assignments
13.16. TRCIDR13 bit assignments
13.17. TRCIMSPEC0 bit assignments
13.18. TRCIDR0 bit assignments
13.19. TRCIDR1 bit assignments
13.20. TRCIDR2 bit assignments
13.21. TRCIDR3 bit assignments
13.22. TRCIDR4 bit assignments
13.23. TRCIDR5 bit assignments
13.24. TRCSCTLRn bit assignments
13.25. TRCACATRn bit assignments
13.26. TRCCIDCVR0 bit assignments
13.27. TRCVMIDCVR0 bit assignments
13.28. TRCCIDCCTLR0 bit assignments
13.29. TRCITMISCOUT bit assignments
13.30. TRCITMISCIN bit assignments
13.31. TRCITATBDATA0 bit assignments
13.32. TRCITATBCTR2 bit assignments
13.33. TRCITATBCTR1 bit assignments
13.34. TRCITATBCTR0 bit assignments
13.35. TRCITCTRL bit assignments
13.36. TRCPIDR0 bit assignments
13.37. TRCPIDR1 bit assignments
13.38. TRCPIDR2 bit assignments
13.39. TRCPIDR3 bit assignments
13.40. TRCPIDR4 bit assignments
13.41. TRCCIDR0 bit assignments
13.42. TRCCIDR1 bit assignments
13.43. TRCCIDR2 bit assignments
13.44. TRCCIDR3 bit assignments
14.1. FPCR bit assignments
14.2. FPSR bit assignments
14.3. MVFR0_EL1 bit assignments
14.4. MVFR1_EL1 bit assignments
14.5. MVFR2_EL1 bit assignments
14.6. FPEXC32_EL2 bit assignments
14.7. FPSID bit assignments
14.8. FPSCR bit assignments

List of Tables

1. Typographical conventions
1.1. Cortex-A57 MPCore multiprocessor implementation options
1.2. Valid combinations of L2 Tag and Data RAM register slice
2.1. Areas that the reset signals control
2.2. Valid reset combinations
2.3. Valid power modes
3.1. AArch64 Stack Pointer options
3.2. AArch32 processor modes and associated Exception levels
3.3. Summary of Jazelle registers
4.1. AArch64 identification registers
4.2. AArch64 exception handling registers
4.3. AArch64 virtual memory control registers
4.4. AArch64 other System registers
4.5. AArch64 cache maintenance operations
4.6. AArch64 TLB maintenance operations
4.7. AArch64 address translation register
4.8. AArch64 address translation operations
4.9. AArch64 miscellaneous System operations
4.10. AArch64 Performance Monitors registers
4.11. AArch64 reset registers
4.12. AArch64 security registers
4.13. AArch64 virtualization registers
4.14. AArch64 TLB maintenance operations
4.15. AArch64 implementation defined registers
4.16. MIDR_EL1 bit assignments
4.17. MPIDR_EL1 bit assignments
4.18. REVIDR_EL1 bit assignments
4.19. ID_PFR0_EL1 bit assignments
4.20. ID_PFR1_EL1 bit assignments
4.21. ID_DFR0_EL1 bit assignments
4.22. ID_MMFR0_EL1 bit assignments
4.23. ID_MMFR1_EL1 bit assignments
4.24. ID_MMFR2_EL1 bit assignments
4.25. ID_MMFR3_EL1 bit assignments
4.26. ID_ISAR0_EL1 bit assignments
4.27. ID_ISAR1_EL1 bit assignments
4.28. ID_ISAR2_EL1 bit assignments
4.29. ID_ISAR3_EL1 bit assignments
4.30. ID_ISAR4_EL1 bit assignments
4.31. ID_ISAR5_EL1 bit assignments
4.32. ID_AA64PFR0_EL1 bit assignments
4.33. ID_AA64DFR0_EL1 bit assignments
4.34. ID_AA64ISAR0_EL1 bit assignments
4.35. ID_AA64MMFR0_EL1 bit assignments
4.36. CCSIDR_EL1 bit assignments
4.37. Encoding of the Cache Size ID Register
4.38. CLIDR_EL1 bit assignments
4.39. CSSELR_EL1 bit assignments
4.40. CTR_EL0 bit assignments
4.41. DCZID_EL0 bit assignments
4.42. VPIDR_EL2 bit assignments
4.43. VMPIDR_EL2 bit assignments
4.44. SCTLR_EL1 bit assignments
4.45. CPACR_EL1 bit assignments
4.46. ACTLR_EL2 bit assignments
4.47. HCR_EL2 bit assignments
4.48. CPTR_EL2 bit assignments
4.49. HSTR_EL2 bit assignments
4.50. SCTLR_EL3 bit assignments
4.51. ACTLR_EL3 bit assignments
4.52. CPTR_EL3 bit assignments
4.53. TCR_EL1 bit assignments
4.54. TCR_EL2 bit assignments
4.55. VTCR_EL2 bit assignments
4.56. TTBR0_EL1 bit assignments
4.57. TTBR0_EL3 bit assignments
4.58. TTBR1_EL1 bit assignments
4.59. TCR_EL3 bit assignments
4.60. ESR_EL1 and ESR_EL3 bit assignments
4.61. IFSR32_EL2 bit assignments for Short-descriptor translation table format
4.62. IFSR32_EL2 bit assignments for Long-descriptor translation table format
4.63. Encodings of LL bits associated with the MMU fault
4.64. ESR_EL2 bit assignments
4.65. PAR_EL1 pass bit assignments
4.66. PAR_EL1 fail bit assignments
4.67. L2CTLR_EL1 bit assignments
4.68. L2ECTLR_EL1 bit assignments
4.69. RVBAR_EL3 bit assignments
4.70. RMR_EL3 bit assignments
4.71. IL1DATAn_EL1 bit assignments
4.72. DL1DATAn_EL1 bit assignments
4.73. RAMINDEX bit assignments
4.74. L2ACTLR_EL1 bit assignments
4.75. CPUACTLR_EL1[63:32] bit assignments
4.76. CPUACTLR_EL1[31:0] bit assignments
4.77. CPUECTLR_EL1 bit assignments
4.78. CPUMERRSR_EL1 bit assignments
4.79. L2MERRSR_EL1 bit assignments
4.80. CBAR_EL1 bit assignments
4.81. Column headings definition for System register summary tables
4.82. c0 register summary
4.83. c1 register summary
4.84. c2 register summary
4.85. c3 register summary
4.86. c5 register summary
4.87. c6 register summary
4.88. c7 register summary
4.89. c7 System operation summary
4.90. c8 System operations summary
4.91. c9 register summary
4.92. c10 register summary
4.93. c12 register summary
4.94. c13 register summary
4.95. c14 register summary
4.96. c15 register summary
4.97. 64-bit register summary
4.98. Identification registers
4.99. CPUID registers
4.100. Virtual memory control registers
4.101. Fault and Exception handling registers
4.102. Other System registers
4.103. Cache and branch predictor maintenance operations
4.104. TLB maintenance operations
4.105. Address translation register
4.106. Address translation operations
4.107. Miscellaneous System operations
4.108. Performance Monitors registers
4.109. Security registers
4.110. Virtualization registers
4.111. Hyp mode TLB maintenance operations
4.112. Implementation defined registers
4.113. TLBTR bit assignments
4.114. MPIDR bit assignments
4.115. VMPIDR bit assignments
4.116. SCTLR bit assignments
4.117. CPACR bit assignments
4.118. SCR bit assignments
4.119. NSACR bit assignments
4.120. SDCR bit assignments
4.121. HCR bit assignments
4.122. HCR2 bit assignments
4.123. HDCR bit assignments
4.124. HCPTR bit assignments
4.125. DFSR bit assignments for Short-descriptor translation table format
4.126. DFSR bit assignments for Long-descriptor translation table format
4.127. Encodings of LL bits associated with the MMU fault
4.128. CBAR bit assignments
6.1. Memory attribute combinations
6.2. L1 RAM memories
7.1. L2 Tag RAM latency with slice and setup factored in
7.2. L2 Data RAM latency with slice and setup factored in
7.3. L2 RAM memories
7.4. L2 memory interface attributes
7.5. External memory attributes
7.6. Use of WRAP and INCR burst types
8.1. Cortex-A57 MPCore multiprocessor GIC memory map
8.2. GIC CPU interface memory-mapped register summary
8.3. AArch32 GIC CPU interface System register summary
8.4. AArch64 GIC CPU interface System register summary
8.5. Active Priority Register implementation
8.6. GICC_IIDR bit assignments
8.7. Active Priority Group0 Register implementation
8.8. Active Priority Group1 Register implementation
8.9. Virtual interface control register summary
8.10. AArch32 virtual interface System register summary
8.11. AArch64 virtual interface System register summary
8.12. GICH_VTR bit assignments
8.13. ICH_VTR_EL2 bit assignments
8.14. Virtual CPU interface register summary
9.1. Generic Timer signals
9.2. AArch64 Generic Timer registers
9.3. AArch32 Generic Timer registers
10.1. External register access conditions
10.2. External register access conditions example
10.3. AArch64 debug register summary
10.4. DBGBCRn_EL1 bit assignments
10.5. DBGWCRn_EL1 bit assignments
10.6. AArch32 debug register summary
10.7. DBGDIDR bit assignments
10.8. DBGDEVID1 bit assignments
10.9. DBGDEVID bit assignments
10.10. Memory-mapped debug register summary
10.11. EDRCR bit assignments
10.12. EDACR bit assignments
10.13. EDITOCTRL bit assignments
10.14. EDITISR bit assignments
10.15. EDITCTRL bit assignments
10.16. EDDEVID1 bit assignments
10.17. EDDEVID bit assignments
10.18. Summary of the Debug Peripheral Identification Registers
10.19. EDPIDR0 bit assignments
10.20. EDPIDR1 bit assignments
10.21. EDPIDR2 bit assignments
10.22. EDPIDR3 bit assignments
10.23. EDPIDR4 bit assignments
10.24. Summary of the Debug Component Identification Registers
10.25. EDCIDR0 bit assignments
10.26. EDCIDR1 bit assignments
10.27. EDCIDR2 bit assignments
10.28. EDCIDR3 bit assignments
10.29. Address mapping for debug trace components
10.30. ROM table registers
10.31. ROMENTRY bit assignments
10.32. ROMENTRY values
10.33. Summary of the ROM table Debug Peripheral Identification Registers
10.34. ROMPIDR0 bit assignments
10.35. ROMPIDR1 bit assignments
10.36. ROMPIDR2 bit assignments
10.37. ROMPIDR3 bit assignments
10.38. ROMPIDR4 bit assignments
10.39. Summary of the ROM table Debug component Identification registers
10.40. ROMCIDR0 bit assignments
10.41. ROMCIDR1 bit assignments
10.42. ROMCIDR2 bit assignments
10.43. ROMCIDR3 bit assignments
11.1. External register access conditions
11.2. External register access conditions example
11.3. PMU register summary in AArch64 state
11.4. PMCR_EL0 bit assignments
11.5. Common Event Identification Register 0 bit assignments
11.6. PMU register summary in AArch32 state
11.7. Memory-mapped PMU register summary
11.8. PMCR_EL0 bit assignments, memory-mapped view
11.9. PMSSR bit assignments
11.10. PMSCR bit assignments
11.11. PMSRR bit assignments
11.12. PMCFGR bit assignments
11.13. Summary of the PMU Peripheral Identification Registers
11.14. PMPIDR0 bit assignments
11.15. PMPIDR1 bit assignments
11.16. PMPIDR2 bit assignments
11.17. PMPIDR3 bit assignments
11.18. PMPIDR4 bit assignments
11.19. Summary of the PMU Component Identification Registers
11.20. PMCIDR0 bit assignments
11.21. PMCIDR1 bit assignments
11.22. PMCIDR2 bit assignments
11.23. PMCIDR3 bit assignments
11.24. PMU events
12.1. Trigger inputs
12.2. Trigger outputs
12.3. Cross trigger register summary
12.4. External register access conditions
12.5. External register access conditions example
12.6. CTIDEVID bit assignments
12.7. CTIITCTRL bit assignment
12.8. CTIITCHINACK bit assignments
12.9. CTIITTRIGINACK bit assignments
12.10. CTIITCHOUT bit assignments
12.11. CTIITTRIGOUT bit assignments
12.12. CTIITCHOUTACK bit assignments
12.13. CTIITTRIGOUTACK bit assignments
12.14. CTIITCHIN bit assignments
12.15. CTIITTRIGIN bit assignments
12.16. Summary of the CTI Peripheral Identification Registers
12.17. CTIPIDR0 bit assignments
12.18. CTIPIDR1 bit assignments
12.19. CTI PIDR2 bit assignments
12.20. CTIPIDR3 bit assignments
12.21. CTIPIDR4 bit assignments
12.22. Summary of the CTI Component Identification Registers
12.23. CTICIDR0 bit assignments
12.24. CTICIDR1 bit assignments
12.25. CTICIDR2 bit assignments
12.26. CTICIDR3 bit assignments
13.1. ETM trace generation options implemented
13.2. ETM resources implemented
13.3. ETM register summary
13.4. TRCCONFIGR bit assignments
13.5. TRCAUXCTLR bit assignments
13.6. TRCEVENTCL0R bit assignments
13.7. TRCEVENTCL1R bit assignments
13.8. TRCSYNCPR bit assignments
13.9. TRCCCCTLR bit assignments
13.10. TRCTRACEIDR bit assignments
13.11. TRCVICTLR bit assignments
13.12. TRCEXTINSELR bit assignments
13.13. TRCIDR8 bit assignments
13.14. TRCID9 bit assignments
13.15. TRCID10 bit assignments
13.16. TRCID11 bit assignments
13.17. TRCID12 bit assignments
13.18. TRCID13 bit assignments
13.19. TRCIMSPEC0 bit assignments
13.20. TRCIDR0 bit assignments
13.21. TRCIDR1 bit assignments
13.22. TRCIDR2 bit assignments
13.23. TRCIDR3 bit assignments
13.24. TRCIDR4 bit assignments
13.25. TRCIDR5 bit assignments
13.26. TRCSCTLRn bit assignments
13.27. TRCACATRn bit assignments
13.28. TRCCIDCVR0 bit assignments
13.29. TRCVMIDCVR0 bit assignments
13.30. TRCCIDCCTLR0 bit assignments
13.31. TRCITMISCOUT bit assignments
13.32. TRCITMISCIN bit assignments
13.33. TRCITATBDATA0 bit assignments
13.34. TRCITATBCTR2 bit assignments
13.35. TRCITATBCTR1 bit assignments
13.36. TRCITATBCTR0 bit assignments
13.37. TRCITCTRL bit assignments
13.38. Summary of the Trace Peripheral ID Registers
13.39. TRCPIDR0 bit assignments
13.40. TRCPIDR1 bit assignments
13.41. TRCPIDR2 bit assignments
13.42. TRCPIDR3 bit assignments
13.43. TRCPIDR4 bit assignments
13.44. Summary of the ETM Component Identification Registers
13.45. TRCCIDR0 bit assignments
13.46. TRCCIDR1 bit assignments
13.47. TRCCIDR2 bit assignments
13.48. TRCCIDR3 bit assignments
14.1. Advanced SIMD and Floating-point feature identification registers
14.2. AArch64 Advanced SIMD and Floating-point System registers
14.3. FPCR bit assignments 
14.4. FPSR bit assignments 
14.5. MVFR0_EL1 bit assignments 
14.6. MVFR1_EL1 bit assignments 
14.7. MVFR2_EL1 bit assignments 
14.8. FPEXC32_EL2 bit assignments 
14.9. AArch32 Advanced SIMD and Floating-point System registers
14.10. FPSID bit assignments
14.11. FPSCR bit assignments
A.1. Clock and clock enable signals
A.2. Reset signals
A.3. Configuration inputs
A.4. GIC CPU interface signals
A.5. Generic Timer signals
A.6. Power control signals
A.7. ACE or CHI configuration inputs
A.8. Asynchronous error signals
A.9. CHI clock and configuration signals
A.10. Transmit request virtual channel signals
A.11. Transmit response virtual channel signals
A.12. Transmit data virtual channel signals
A.13. Receive snoop virtual channel signals
A.14. Receive response virtual channel signals
A.15. Receive data virtual channel signals
A.16. System address map signals
A.17. Clock and configuration signals
A.18. Write address channel signals
A.19. Write data channel signals
A.20. Write response channel signals
A.21. Read address channel signals
A.22. Read data channel signals
A.23. Snoop address channel signals
A.24. Snoop response channel signals
A.25. Snoop data channel handshake signals
A.26. Read/write acknowledge signals
A.27. Clock and configuration signals
A.28. Write address channel signals
A.29. Write data channel signals
A.30. Write response channel signals
A.31. Read address channel signals
A.32. Read data channel signals
A.33. APB interface signals
A.34. Authentication interface signals
A.35. Miscellaneous debug signals
A.36. ATB interface signals
A.37. Miscellaneous ETM interface signal
A.38. Cross trigger channel interface signals
A.39. Performance monitoring signals
A.40. DFT interface signals
A.41. MBIST interface signals
C.1. Issue A
C.2. Differences between Issue A and Issue B
C.3. Differences between Issue B and Issue C

Proprietary Notice

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Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A04 June 2013First release for r0p0
Revision B04 October 2013First release for r0p1
Revision C09 December 2013First release for r1p0
Copyright © 2013 ARM. All rights reserved.ARM DDI 0488C