A.7. Power control signals

Table A.6 shows the power control signals.

Table A.6. Power control signals

SignalTypeDescription
EVENTIInput

Event input for processor wake-up from WFE low-power state. When this signal is asserted, it acts as a WFE wake-up event to all the processors in the MPCore device. This signal must be asserted for at least one CLK cycle. See Event communication using WFE and SEV instructions for more information.

EVENTOOutput

Event output. This signal is asserted HIGH for three CLK cycles when any of the processors in the MPCore device executes an SEV instruction. See Event communication using WFE and SEV instructions for more information.

CLREXMONREQInput

Clearing of the external global exclusive monitor request. When this signal is asserted, it acts as a WFE wake-up event to all the processors in the MPCore device. See CLREXMON request and acknowledge signaling for more information.

CLREXMONACKOutput

Clearing of the external global exclusive monitor acknowledge. See CLREXMON request and acknowledge signaling for more information.

STANDBYWFE[N:0]Output

Indicates whether a processor is in WFE low-power state:

0

Processor not in WFE low-power state.

1

Processor in WFE low-power state.

STANDBYWFI[N:0]Output

Indicates whether a processor is in WFI low-power state:

0

Processor not in WFI low-power state.

1

Processor in WFI low-power state.

STANDBYWFIL2Output

Indicates whether the L2 is in WFI low-power state. This signal is active when the following are true:

  • All processors are in WFI low-power state.

  • ACINACTM or SINACT and AINACTS are asserted HIGH.

  • L2 memory system is idle.

L2FLUSHREQInput

L2 hardware flush request. This signal indicates:

0

L2 hardware flush request is not asserted.

1

L2 hardware flush request is asserted.

L2FLUSHDONEOutput

L2 hardware flush done.

0

L2 hardware flush is not finished.

1

L2 hardware flush is finished.

SMPEN[N:0]Output

CPUECTLR.SMPEN output. This signal indicates:

0

The CPUECTLR.SMPEN bit is not set.

1

The CPUECTLR.SMPEN bit is set.

See CPU Extended Control Register, EL1 for more information.

CPUQACTIVE[N:0]Output

When HIGH, it indicates that processor N is active. See Processor dynamic retention for more information.

CPUQREQn[N:0]Input

The power controller sets this signal LOW, to request that processor N enters retention state.

CPUQACCEPTn[N:0]Output

This signal goes LOW, if processor N accepts the power controller retention request.

CPUQDENY[N:0]Output

When HIGH, it indicates that processor N denies the power controller retention request.

L2QACTIVEOutput

When HIGH, it indicates that the L2 Data and Tag RAMs are active. See L2 RAMs dynamic retention for more information.

L2QREQnInput

The power controller sets this signal LOW, to request that the L2 Data and Tag RAMs enter retention state.

L2QACCEPTnOutput

This signal goes LOW, if the L2 Data and Tag RAMs accept the power controller retention request.

L2QDENYOutput

When HIGH, it indicates that the L2 Data and Tag RAMs deny the power controller retention request.


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