A.1. About the signal descriptions

The tables in this appendix list the Cortex-A57 MPCore multiprocessor signals, along with their direction, input or output, and a high-level description.

Some of the buses include a configurable width field, <signal>[N:0], where N = 0, 1, 2, or 3, to encode up to four processors. For example:

Some signals are specified in the form <signal>x, where x = 0, 1, 2 or 3 references processor 0, processor 1, processor 2, or processor 3, respectively. If a processor is not present, the corresponding pin is removed. For example:

The number of signals changes depending on the configuration. For example, the CHI interface signals are not present when the processor is configured to have an ACE interface.

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