8.3.4. Virtual interface control register summary

The virtual interface control registers are management registers. The multiprocessor configuration software must ensure that these registers are accessible only by a hypervisor, or similar software.

Virtual interface control register summary

Table 8.9 shows the register map for the virtual interface control registers. The offsets in this table are relative to the virtual interface control registers block base address as shown in Table 8.1.

All the registers in Table 8.9 are word-accessible. Registers not described in this table are Reserved.

Table 8.9. Virtual interface control register summary

OffsetNameTypeResetDescription
0x000GICH_HCRRW0x00000000Hypervisor Control Register [a]
0x004GICH_VTRRO0x90000003VGIC Type Memory-Mapped Register
0x008GICH_VMCRRW0x004C0000

Virtual Machine Control Register [a]

0x010GICH_MISRRO0x00000000

Maintenance Interrupt Status Register [a]

0x020GICH_EISR0RO0x00000000

End of Interrupt Status Register [a]

0x030GICH_ELSR0RO0x0000000F

Empty List Register Status Register [a]

0x0F0GICH_APRRW0x00000000Active Priorities Register [a]
0x100GICH_LR0RW0x00000000List Register 0 [a]
0x104GICH_LR1RW0x00000000List Register 1 [a]
0x108GICH_LR2RW0x00000000List Register 2 [a]
0x10CGICH_LR3RW0x00000000List Register 3 [a]

[a] See the ARM® Generic Interrupt Controller Architecture Specification GICv3 for more information.


AArch32 virtual interface System register summary

Table 8.10 shows the register map for the AArch32 virtual interface System registers. The offsets in this table are relative to the virtual interface control registers block base address as shown in Table 8.1.

All the registers in Table 8.10 are word-accessible. Registers not described in this table are Reserved.

Table 8.10. AArch32 virtual interface System register summary

NameCRnop1CRmop2TypeDescription
ICH_APR0c124c80RWHypervisor Active Priority Register 0
ICH_APR1  c90RWHypervisor Active Priority Register 1
ICH_VSEIR  4RWVirtual System Error Interrupt Register
ICH_SRE  5RWHypervisor System Register
ICH_HCR 4c110RWHypervisor Control Register
ICH_VTR  1ROVGIC Type Register
ICH_MISR  2ROMaintenance Interrupt Status Register
ICH_EISR  3ROEnd of Interrupt Status Register
ICH_ELSR  5ROEmpty List Register Status Register
ICH_VMCR  7RWVirtual Machine Control Register
ICH_LR0  c120RWList Register 0 to 3
ICH_LR1   1RW
ICH_LR2   2RW
ICH_LR3   3RW
ICH_LRC0  c140RWList Register Extension 0 to 3
ICH_LRC1   1RW
ICH_LRC2   2RW
ICH_LRC3   3RW

AArch64 virtual interface System register summary

Table 8.11 shows the register map for the AArch64 virtual interface System registers. The offsets in this table are relative to the virtual interface control registers block base address as shown in Table 8.1.

All the registers in Table 8.11 are word-accessible. Registers not described in this table are Reserved.

Table 8.11. AArch64 virtual interface System register summary

NameTypeDescription
ICH_APR0_EL2RWHypervisor Active Priority Register
ICH_VSEIR_EL2RWVirtual System Error Interrupt Register
ICH_HCR_EL2RWHypervisor Control Register
ICH_VTR_EL2ROVGIC Type Register
ICC_SRE_EL2RWHypervisor System Register Enable
ICH_MISR_EL2ROMaintenance Interrupt Status Register
ICH_EISR_EL2ROEnd of Interrupt Status Register
ICH_ELSR_EL2ROEmpty List Register Status Register
ICH_VMCR_EL2RWVirtual Machine Control Register
ICH_LR0_EL2RWList Register 0
ICH_LR1_EL2RWList Register 1
ICH_LR2_EL2RWList Register 2
ICH_LR3_EL2RWList Register 3

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