ARM Cortex-A57 MPCore Processor Technical Reference Manual: 8.3.4. Virtual interface control register summary

8.3.4. Virtual interface control register summary

The virtual interface control registers are management registers. The multiprocessor configuration software must ensure that these registers are accessible only by a hypervisor, or similar software.

Virtual interface control register summary

Table 8.9 shows the register map for the virtual interface control registers. The offsets in this table are relative to the virtual interface control registers block base address as shown in Table 8.1.

All the registers in Table 8.9 are word-accessible. Registers not described in this table are Reserved.

Table 8.9. Virtual interface control register summary

Offset	Name	Type	Reset	Description
`0x000`	GICH_HCR	RW	`0x00000000`	Hypervisor Control Register ^[a]
`0x004`	GICH_VTR	RO	`0x90000003`	VGIC Type Memory-Mapped Register
`0x008`	GICH_VMCR	RW	`0x004C0000`	Virtual Machine Control Register ^[a]
`0x010`	GICH_MISR	RO	`0x00000000`	Maintenance Interrupt Status Register ^[a]
`0x020`	GICH_EISR0	RO	`0x00000000`	End of Interrupt Status Register ^[a]
`0x030`	GICH_ELSR0	RO	`0x0000000F`	Empty List Register Status Register ^[a]
`0x0F0`	GICH_APR	RW	`0x00000000`	Active Priorities Register ^[a]
`0x100`	GICH_LR0	RW	`0x00000000`	List Register 0 ^[a]
`0x104`	GICH_LR1	RW	`0x00000000`	List Register 1 ^[a]
`0x108`	GICH_LR2	RW	`0x00000000`	List Register 2 ^[a]
`0x10C`	GICH_LR3	RW	`0x00000000`	List Register 3 ^[a]
^[a]See the ARM^® Generic Interrupt Controller Architecture Specification GICv3 for more information.

AArch32 virtual interface System register summary

Table 8.10 shows the register map for the AArch32 virtual interface System registers. The offsets in this table are relative to the virtual interface control registers block base address as shown in Table 8.1.

All the registers in Table 8.10 are word-accessible. Registers not described in this table are Reserved.

Table 8.10. AArch32 virtual interface System register summary

Name	CRn	op1	CRm	op2	Type	Description
ICH_APR0	c12	4	c8	0	RW	Hypervisor Active Priority Register 0
ICH_APR1			c9	0	RW	Hypervisor Active Priority Register 1
ICH_VSEIR				4	RW	Virtual System Error Interrupt Register
ICH_SRE				5	RW	Hypervisor System Register
ICH_HCR		4	c11	0	RW	Hypervisor Control Register
ICH_VTR				1	RO	VGIC Type Register
ICH_MISR				2	RO	Maintenance Interrupt Status Register
ICH_EISR				3	RO	End of Interrupt Status Register
ICH_ELSR				5	RO	Empty List Register Status Register
ICH_VMCR				7	RW	Virtual Machine Control Register
ICH_LR0			c12	0	RW	List Register 0 to 3
ICH_LR1				1	RW
ICH_LR2				2	RW
ICH_LR3				3	RW
ICH_LRC0			c14	0	RW	List Register Extension 0 to 3
ICH_LRC1				1	RW
ICH_LRC2				2	RW
ICH_LRC3				3	RW

AArch64 virtual interface System register summary

Table 8.11 shows the register map for the AArch64 virtual interface System registers. The offsets in this table are relative to the virtual interface control registers block base address as shown in Table 8.1.

All the registers in Table 8.11 are word-accessible. Registers not described in this table are Reserved.

Table 8.11. AArch64 virtual interface System register summary

Name	Type	Description
ICH_APR0_EL2	RW	Hypervisor Active Priority Register
ICH_VSEIR_EL2	RW	Virtual System Error Interrupt Register
ICH_HCR_EL2	RW	Hypervisor Control Register
ICH_VTR_EL2	RO	VGIC Type Register
ICC_SRE_EL2	RW	Hypervisor System Register Enable
ICH_MISR_EL2	RO	Maintenance Interrupt Status Register
ICH_EISR_EL2	RO	End of Interrupt Status Register
ICH_ELSR_EL2	RO	Empty List Register Status Register
ICH_VMCR_EL2	RW	Virtual Machine Control Register
ICH_LR0_EL2	RW	List Register 0
ICH_LR1_EL2	RW	List Register 1
ICH_LR2_EL2	RW	List Register 2
ICH_LR3_EL2	RW	List Register 3

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