A.10.2. Write address channel signals

Table A.18 shows the write address channel signals for the ACE master interface.

Table A.18. Write address channel signals

SignalTypeDescription
AWREADYMInput

Write address ready.

AWVALIDMOutput

Write address valid.

AWIDM[5:0]Output

Write request ID.

AWADDRM[43:0]OutputWrite address.
AWLENM[7:0]Output

Write burst length. AWLENM[7:2] is always 0b000000.

AWSIZEM[2:0]Output

Write burst size.

AWBURSTM[1:0]Output

Write burst type.

AWBARM[1:0]OutputWrite barrier type.
AWDOMAINM[1:0]OutputWrite shareability domain type.
AWLOCKMOutput

Write lock type.

AWCACHEM[3:0]Output

Write cache type.[a]

AWPROTM[2:0]Output

Write protection type.

AWSNOOPM[2:0]Output

Write snoop request type.

AWUNIQUEMOutput

Indicates the write operation for a WriteBack, WriteClean, or WriteEvict transaction is:

0

Shared.

1

Unique.

WRMEMATTR[7:0]Output

Write request raw memory attributes:

[7]

Outer Shareable.

[6:3]

Outer memory attribute in MAIR format.

[2]

Inner Shareable.

[1:0]
0b00

Device.

0b01

Normal Non-cacheable.

0b10

Normal Write-Through.

0b11

Normal Write-Back.

[a] Allocation hints based on outer memory attributes from the MMU.


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