7.2.3. Enabling and disabling the L2 cache

For processor requests, the L2 cache is enabled when the C bit of the SCTLR register is enabled, see System Control Register. The cache attributes are provided with each request, taking into account the page attributes that the MMU page tables provided and overriding these attributes if the corresponding cache enable bit in the SCTLR is disabled.

To enable the L2 cache to cache both instructions and data following the reset sequence, you must:

  1. Complete the processor reset sequence.

  2. Enable L2 ECC, if required by programming bit[21] of the L2 Control Register. See L2 Control Register, EL1.

  3. Program the I bit and C bit of the SCTLR.

To disable the L2 cache, you must use the following sequence:

  1. Disable the C bit.

  2. Clean and invalidate the L1 and L2 caches.

For ACP requests, the L2 cache is enabled if the request uses Normal Write-Back memory attributes. The processor searches the L2 cache to determine if the request is valid before allocating the line for Normal Write-Back Read-Write-Allocate memory.

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