8.3.1. CPU interface register summary

Each GIC CPU interface block provides the interface for an Cortex-A57 MPCore processor that operates with the GIC. Each CPU interface provides a programming interface for:

For more information on CPU interfaces, see the ARM® Generic Interrupt Controller Architecture Specification, GICv3.

AArch32 GIC CPU interface memory-mapped register summary

Table 8.2 shows the GIC CPU interface register address offsets of the Cortex-A57 MPCore processor. For information about an external standalone GIC such as the ARM GIC-400 or other proprietary GIC, see the documentation of that product.

Table 8.2 shows the register memory map for the CPU interface in AArch32. The offsets in this table are relative to the CPU interface block base address as shown in Table 8.1.

All the registers in Table 8.2 are word-accessible. Registers not described in this table are Reserved.

Table 8.2. GIC CPU interface memory-mapped register summary

OffsetNameTypeResetDescription
0x0000GICC_CTLRRW0x00000000CPU Interface Control Register [a]
0x0004GICC_PMRRW0x00000000Interrupt Priority Mask Register [a]
0x0008GICC_BPRRW

0x00000002 (S)[b]

0x00000003 (NS)[c]

Binary Point Register [a]
0x000CGICC_IARRO0x000003FFInterrupt Acknowledge Register [a]
0x0010GICC_EOIRWO-End Of Interrupt Register [a]
0x0014GICC_RPRRO0x000000FFRunning Priority Register [a]
0x0018GICC_HPPIRRO0x000003FFHighest Priority Pending Interrupt Register [a]
0x001CGICC_ABPRRW0x00000003Aliased Binary Point Register [a]
0x0020GICC_AIARRO0x000003FF

Aliased Interrupt Acknowledge Register [a]

0x0024GICC_AEOIRWO-

Aliased End of Interrupt Register [a]

0x0028GICC_AHPPIRRO0x000003FF

Aliased Highest Priority Pending Interrupt Register [a]

0x00D0GICC_APR0RW0x00000000Active Priority Register
0x00E0GICC_NSAPR0RW0x00000000Non-secure Active Priority Register
0x00FCGICC_IIDRRO0x0074043BCPU Interface Identification Register
0x1000GICC_DIRWO-Deactivate Interrupt Register [a]

[a] See the ARM® Generic Interrupt Controller Architecture Specification, GICv3 for more information.

[b] S = Secure.

[c] NS = Non-secure.


AArch32 GIC CPU interface System register summary

Table 8.3 shows the System register map for the CPU interface in AArch32. See the ARM® Generic Interrupt Controller Architecture Specification, GICv3 for more information about the registers.

Table 8.3. AArch32 GIC CPU interface System register summary

NameCRnop1CRmop2TypeDescription
ICC_PMRc40c60RWPriority Mask Register
ICC_IAR0c120c80ROGroup0 Interrupt Acknowledge Register
ICC_EOIR0  1WOGroup0 End of Interrupt Register
ICC_HPPIR0  2ROGroup0 Highest Priority Pending Interrupt Register
ICC_BPR0  3RWGroup0 Binary Pointer Register
ICC_AP0R0  4RWActive Priority Group0 Register
ICC_AP1R0  c90RWActive Priority Group1 Register
ICC_DIR  c111WODeactivate Register
ICC_RPR  3RORunning Priority Register
ICC_IAR1  c120ROGroup1 Interrupt Acknowledge Register
ICC_EOIR1 1WOGroup1 End of Interrupt Register
ICC_HPPIR1 2ROGroup1 Highest Priority Pending Interrupt Register
ICC_BPR1 3RW B[a]Group1 Binary Pointer Register
ICC_CTLR 4RW B[a]Control Register
ICC_SRE 5RW B[a]System Register Enable
ICC_IGRPEN0 6RWGroup0 Interrupt Group Enable
ICC_IGRPEN1 7RW B[a]Group1 Interrupt Group Enable
ICC_SGI1R[b] -WOGroup1 Software Generated Interrupt Register
ICC_ASGI1R[b] 0c12-WOAliased Group1 Software Generated Interrupt Register
ICC_SGI0R[b] 2c12-WOGroup0 Software Generated Interrupt Register
ICC_MCTLR 6c124RWMonitor Control Register
ICC_MSRE  5RWMonitor System Register Enable
ICC_MGRPEN1  7RWMonitor Group1 Interrupt Group Enable

[a] When operating in EL3, accesses to Banked EL1 registers access the copy designated by the current value of the SCR_EL3.NS. When EL3 is using AArch32, there is no Secure EL1 interrupt regime and accesses in any Secure EL3 mode, except Monitor mode, access the Secure copy.

[b] Use MCRR instructions to access this register in AArch32 state.


AArch64 GIC CPU interface System register summary

Table 8.4 shows the System register map for the GIC CPU interface in AArch64. See the ARM® Generic Interrupt Controller Architecture Specification, GICv3 for more information about the registers.

Table 8.4. AArch64 GIC CPU interface System register summary

NameTypeDescription
ICC_PMR_EL1RWPriority Mask Register
ICC_IAR0_EL1ROGroup0 Interrupt Acknowledge Register
ICC_EOIR0_EL1WOGroup0 End of Interrupt Register
ICC_HPPIR0_EL1ROGroup0 Highest Priority Pending Interrupt Register
ICC_BPR0_EL1RWGroup0 Binary Pointer Register
ICC_AP0R0_EL1RWActive Priority Group0 Register
ICC_AP1R0_EL1RWActive Priority Group1 Register
   
ICC_DIR_EL1WODeactivate Register
ICC_RPR_EL1RORunning Priority Register
ICC_SGI1R_EL1WOGroup1 Software Generated Interrupt Register
ICC_ASGI1R_EL1WOAliased Group1 Software Generated Interrupt Register
ICC_SGI0R_EL1WOGroup0 Software Generated Interrupt Register
ICC_IAR1_EL1ROGroup1 Interrupt Acknowledge Register
ICC_EOIR1_EL1WOGroup1 End of Interrupt Register
ICC_HPPIR1_EL1ROGroup1 Highest Priority Pending Interrupt Register
ICC_BPR1_EL1RW B[a]Group1 Binary Pointer Register
ICC_CTLR_EL1RW BControl Register
ICC_SRE_EL1RW BSystem Register Enable
ICC_IGRPEN0_EL1RWGroup0 Interrupt Group Enable Register
ICC_IGRPEN1_EL1RW BGroup1 Interrupt Group Enable
ICC_CTLR_EL3RWEL3 Control Register
ICC_SRE_EL3RWEL3 System Register Enable
ICC_GRPEN1_EL3RWEL3 Group1 Interrupt Group Enable

[a] When operating in EL3, accesses to Banked EL1 registers access the copy designated by the current value of the SCR_EL3.NS. When EL3 is using AArch32, there is no Secure EL1 interrupt regime and accesses in any Secure EL3 mode, except Monitor mode, access the Secure copy.


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