10.10.1. Debug memory map

The memory map supports up to four processors in an MPCore device. Table 10.29 shows the address mapping for the debug trace components.

Table 10.29. Address mapping for debug trace components

Address rangeComponent [a]
0x000000 - 0x00FFFFROM table
0x010000 - 0x01FFFFProcessor 0 Debug
0x020000 - 0x02FFFFProcessor 0 CTI
0x030000 - 0x03FFFFProcessor 0 PMU
0x040000 - 0x04FFFFProcessor 0 Trace
0x050000 - 0x10FFFFReserved
0x110000 - 0x11FFFFProcessor 1 Debug
0x120000 - 0x12FFFFProcessor 1 CTI
0x130000 - 0x13FFFFProcessor 1 PMU
0x140000 - 0x14FFFFProcessor 1 Trace
0x150000 - 0x20FFFFReserved
0x210000 - 0x21FFFFProcessor 2 Debug
0x220000 - 0x22FFFFProcessor 2 CTI
0x230000 - 0x23FFFFProcessor 2 PMU
0x240000 - 0x24FFFFProcessor 2 Trace
0x250000 - 0x30FFFFReserved
0x310000 - 0x31FFFFProcessor 3 Debug
0x320000 - 0x32FFFFProcessor 3 CTI
0x330000 - 0x33FFFFProcessor 3 PMU
0x340000 - 0x34FFFFProcessor 3 Trace
0x350000 - 0x3FFFFFReserved

[a] Indicates the mapped component if present, otherwise reserved.


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