A.12.3. Miscellaneous debug signals

Table A.35 shows the miscellaneous debug signals.

Table A.35. Miscellaneous debug signals

SignalTypeDescription
DBGROMADDR[43:12]Input

Specifies bits[43:12] of the top-level ROM table Physical Address.

If the address cannot be determined, tie this signal LOW.

This signal is only sampled during powerup reset of the processor.

DBGROMADDRVInput

Valid signal for DBGROMADDR.

If the address cannot be determined, tie this signal LOW.

This signal is only sampled during powerup reset of the processor.

DBGACK[N:0]Output

Debug acknowledge:

0

Debug not acknowledged.

1

Debug acknowledged.

nCOMMIRQ[N:0]Output

Communications channel receive or transmit interrupt request, active LOW:

0

Receive section data transfer register is full or transmit section data transfer register is empty.

1

Either or both:

  • The receive section data transfer register is empty.

  • The transmit section data transfer register is empty.

COMMRX[N:0]Output

Communications channel receive. Receive portion of Data Transfer Register full flag:

0

Empty.

1

Full.

COMMTX[N:0]Output

Communication channel transmit. Transmit portion of Data Transfer Register empty flag:

0

Full.

1

Empty.

EDBGRQ[N:0]Input

External debug request:

0

No external debug request.

1

External debug request.

The processor treats the EDBGRQ input as level-sensitive. The EDBGRQ input must be asserted until the processor asserts DBGACK.

DBGRSTREQ[N:0]Output

Warm reset request:

0

Warm reset is not requested.

1

Request Warm reset.

This output is controlled by Warm reset request bit in External Debug Power/Reset Control Register, EDPRCR. See WARMRSTREQ and DBGRSTREQ for more information.

DBGNOPWRDWN[N:0]Output

No powerdown request. On a powerdown request:

0

The SoC power controller powers down the processor.

1

The SoC power controller does not power down the processor.

DBGPWRDUP[N:0]Input

Processor power status:

0

Processor is not powered up.

1

Processor is powered up.

See External debug over powerdown for more information.

DBGPWRUPREQ[N:0]Output

Processor powerup request:

0

No request for processor power up.

1

Request for processor power up.

DBGL1RSTDISABLE[a]Input

Disable L1 data cache and L2 snoop tag RAM automatic invalidate on reset functionality.

0

Enable automatic invalidation of L1 data cache and L2 snoop tag RAMs on reset.

1

Disable automatic invalidation of L1 data cache and L2 snoop tag RAMs on reset

This signal is sampled only during reset of the processor.

[a] This signal is available only in r1p0 and later revisions.


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