4.5.16. Hyp Translation Control Register

The processor does not use the implementation defined bit, HTCR[30], so this bit is res0.

The HTCR characteristics are:

Purpose

Controls translation table walks required for the stage 1 translation of memory accesses from Hyp mode, and holds cacheability and shareability information for the accesses.

Usage constraints

The accessibility to the HTCR by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
---RWRW-
Configurations

The HTCR is:

The TCR_EL2 is a 32-bit register in AArch64 state.

Attributes

See the register summary in Table 4.84.

See the ARM® Architecture Reference Manual ARMv8 for more information.

To access the HTCR in AArch32 state, read or write the CP15 register with:

MRC p15, 4, <Rt>, c2, c0, 2; Read Hyp Translation Control Register
MCR p15, 4, <Rt>, c2, c0, 2; Write Hyp Translation Control Register
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