7.7.6. ACE ARID and AWID assignment

When the system issues multiple requests on the AR channel with the same ARID, or on the AW channel with the same AWID, it must follow the appropriate ordering rules as described in the ARM® AMBA® AXI™ and ACE™ Protocol Specification.

For certain transactions, the system must be able to identify which processor generated the request. This applies to requests affecting the global exclusive monitor in addition to Strongly-ordered or Device memory type accesses to peripherals.

ARCACHEM[3:0] and AWCACHEM[3:0] identify whether the memory types are Strongly-ordered, Device, or Normal Non-cacheable. See the ARM® AMBA® AXI™ and ACE™ Protocol Specification. For these memory types, if ARIDM[2] or AWIDM[2] is LOW, then the request is generated from one of the Cortex-A57 MPCore processors. ARIDM[1:0] or AWIDM[1:0] indicate which processor generated the request. If ARIDM[2] or AWIDM[2] is HIGH, the request originates from the master connected to the ACP slave port.

For an exclusive read transaction such as ARLOCK asserted, ARID[1:0] indicates which processor generated the request. Only processors can generate exclusive read requests, and not the ACP or any other source.

For an exclusive write transaction such as AWLOCK asserted, AWID[1:0] indicates which processor generated the request. Only processors can generate exclusive write requests, and not the ACP or any other source.

The system does not rely on specific values of ARID or AWID that correspond with specific transaction sources or transaction types other than the information described in this section.

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