A.12.1. APB interface signals

Table A.33 shows the APB interface signals.

Table A.33. APB interface signals

SignalTypeDescription
PCLKDBGInput

APB clock.

PCLKENDBGInput

APB clock enable.

nPRESETDBGInput

Active-LOW APB reset:

0

Reset APB.

1

Do not reset APB.

PSELDBGInput

Debug registers select:

0

Debug registers not selected.

1

Debug registers selected.

PADDRDBG[21:2]Input

APB address bus bits[21:2].

PADDRDBG31Input

APB address bus bit[31]:

0

Not an external debugger access.

1

External debugger access.

PENABLEDBGInput

Indicates the second and subsequent cycles of an APB transfer.

PWRITEDBGInput

APB read or write signal:

0

Reads from APB.

1

Writes to APB.

PWDATADBG[31:0]Input

APB write data bus.

PRDATADBG[31:0]Output

APB read data bus.

PREADYDBGOutput

APB slave ready. An APB slave can assert PREADYDBG to extend a transfer by inserting wait states.

PSLVERRDBGOutput

APB slave transfer error:

0

No transfer error.

1

Transfer error.


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