4.5.8. Non-secure Access Control Register

The NSACR characteristics are:

Purpose

Defines the Non-secure access permission to the CP10 and CP11 coprocessors and controls Non-secure Advanced SIMD functionality.

Usage constraints

The accessibility to the NSACR by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-ROTRAPRORORW

If EL3 is using AArch64, accesses to this register from Secure EL1 using AArch32 are trapped to EL3.

Configurations

The NSACR:

  • Is a Restricted access register that exists only in the Secure state but can be read from the Non-secure state.

  • Functionality is replaced by the behavior in the CPTR_EL3 register in AArch64 state. See Architectural Feature Trap Register, EL3 for more information.

When EL3 is using AArch64, reads of the NSACR from Non-secure EL2 or Non-secure EL1 using AArch32, return a fixed value of 0x00000C00.

Attributes

See the register summary in Table 4.83.

Figure 4.85 shows the NSACR bit assignments.

Figure 4.85. NSACR bit assignments

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Table 4.119 shows the NSACR bit assignments.

Table 4.119. NSACR bit assignments

BitsNameFunction
[31:21]-

Reserved, res0.

[20]NSTRCDIS

Disable Non-secure access to CP14 trace registers:

0

CP14 access to trace registers is not supported. This bit is res0.

[19:16]-

Reserved, res0.

[15]NSASEDIS

Disables Non-secure Advanced SIMD functionality. The values are:

0

This bit has no effect on the ability to write to the CAPCR.ASEDIS bit. This is the reset value.

1

When executing in Non-secure state, the CPACR.ASEDIS bit is res1.

[14:12]-

Reserved, res0.

[11]cp11

Non-secure access to coprocessor 11 enable. The values are:

0

Secure access only. Any attempt to access coprocessor 11 in Non-secure state results in an Undefined Instruction exception. If the processor is in Non-secure state, the corresponding bits in the CPACR ignore writes and read as 0b00, access denied. This is the reset value.

1

Access from any Security state.

[10]cp10

Non-secure access to coprocessor 10 enable. The values are:

0

Secure access only. Any attempt to access coprocessor 10 in Non-secure state results in an Undefined Instruction exception. If the processor is in Non-secure state, the corresponding bits in the CPACR ignore writes and read as 0b00, access denied. This is the reset value.

1

Access from any Security state.

[9:0]-

Reserved, res0.


To access the NSACR in AArch32 state, read or write the CP15 register with:

MRC p15, 0, <Rt>, c1, c1, 2; Read Non-secure Access Control Register data
MCR p15, 0, <Rt>, c1, c1, 2; Write Non-secure Access Control Register data
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