A.16.1. DFT signals

Table A.40 shows the DFT interface signals.

Table A.40. DFT interface signals

SignalTypeDescription
DFTCLKBYPASSInputBypasses the strobe clock register to the L2 RAMs, forcing the L2 RAMs to be tested using CLK as the source clock
DFTCRCLKDISABLE[N:0]Input

Disables processor clock grid

DFTL2CLKDISABLEInputDisables L2 clock grid
DFTMCPHOLDInput

Disables multi-cycle paths on RAM interfaces

DFTRAMHOLDInputDisables the RAM chip selects during scan shift
DFTRSTDISABLEInput

Disables internal synchronized reset during scan shift

DFTSEInput

Scan shift enable, forces on the clock grids during scan shift


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