4.5.24. Configuration Base Address Register

The CBAR characteristics are:

Purpose

Holds the physical base address of the memory-mapped GIC CPU interface registers.

Usage constraints

The accessibility to the CBAR by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO
Configurations

The CBAR is Common to the Secure and Non-secure states.

Attributes

See the register summary in Table 4.96.

Figure 4.93 shows the CBAR bit assignments.

Figure 4.93. CBAR bit assignments

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Table 4.128 shows the CBAR bit assignments.

Table 4.128. CBAR bit assignments

BitsNameFunction
[31:18]PERIPHBASE[31:18]

The primary input PERIPHBASE[31:18] determines the reset value.

[17:12]-

Reserved, res0.

[11:0]PERIPHBASE[43:32]

The primary input PERIPHBASE[43:32] determines the reset value.


To access the CBAR in AArch32 state, read the CP15 register with:

MRC p15, 1, <Rt>, c15, c3, 0; Read Configuration Base Address Register
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