A.3. Reset signals

Table A.2 shows the reset and reset control signals.

Table A.2. Reset signals

SignalTypeDescription
nCPUPORESET[N:0]Input

Individual processor powerup resets:

0

Apply reset to the processor including Debug, ETM, breakpoint and watchpoint logic.

1

Do not apply reset to the processor.

nCORERESET[N:0]Input

Individual processor reset excluding Debug and ETM:

0

Apply reset to the processor excluding Debug, ETM, breakpoint and watchpoint logic.

1

Do not apply reset to the processor.

WARMRSTREQ[N:0]Output

Individual processor Warm reset request:

0

Do not apply Warm reset to processor.

1

Apply Warm reset to processor.

This output is controlled by Reset request bit in the Reset Management Register (RMR or RMR_EL3). See Resets for more information.

nL2RESETInput

L2 reset:

0

Apply reset to shared L2 memory system controller.

1

Do not apply reset to shared L2 memory system controller.

L2RSTDISABLEInput

Disable automatic L2 cache invalidate at reset:

0

L2 cache is reset by hardware.

1

L2 cache is not reset by hardware.


See Clocking and resets for more information.

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