6.3.6. Hardware L1 I-cache prefetching

The processor implements speculative prefetching on the instruction side. Following an L1 I-cache miss, the next sequential line is looked up in the L1 instruction cache. If a miss is indicated, and no pipeline flushes have occurred, a second L2 request is initiated for the next sequential line. This line is not committed to the instruction cache unless actually demanded by a fetch. This is the default behavior.

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