4.5.3. Multiprocessor Affinity Register

The MPIDR characteristics are:

Purpose

Provides an additional processor identification mechanism for scheduling purposes in a multiprocessor system.

Usage constraints

The accessibility to the MPIDR by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO
Configurations

The MPIDR is:

Attributes

See the register summary in Table 4.82.

Figure 4.80 shows the MPIDR bit assignments.

Figure 4.80. MPIDR bit assignments

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Table 4.114 shows the MPIDR bit assignments.

Table 4.114. MPIDR bit assignments

BitsNameFunction
[31]-Reserved, res1.
[30]U

Indicates a Uniprocessor system, as distinct from processor 0 in a multiprocessor system. This value is:

0

Processor is part of a multiprocessor system.

[29:25]-

Reserved, res0.

[24]MT

Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach:

0

Performance of processors at the lowest affinity level is largely independent.

1

Performance of processors at the lowest affinity level is very interdependent.

[23:16]Cluster ID Aff2

Indicates the value read in at reset, from the CLUSTERIDAFF2 configuration signal. It identifies a Cortex-A57 MPCore device in a system with more than one Cortex-A57 MPCore device present.

[15:8]Cluster ID Aff1

Indicates the value read in at reset, from the CLUSTERIDAFF1 configuration signal. It identifies an Cortex-A57 MPCore device in a system with more than one Cortex-A57 MPCore devices are present.

[7:2]-

Reserved, res0.

[1:0]CPU ID

Indicates the processor number in the Cortex-A57 MPCore device. The possible values are:

0x0

An MPCore device with one processor only.

0x0, 0x1

An MPCore device with two processors.

0x0, 0x1, 0x2

An MPCore device with three processors.

0x0, 0x1, 0x2, 0x3

An MPCore device with four processors.


To access the MPIDR in AArch32 state, read the CP15 registers with:

MRC p15, 0, <Rt>, c0, c0, 5; Read Multiprocessor Affinity Register
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