A.5. GIC CPU interface signals

Table A.4 shows the Generic Interrupt Controller (GIC) CPU interface signals.

Table A.4. GIC CPU interface signals

SignalTypeDescription
nIRQ[N:0]Input

Individual processor IRQ request input. Active-LOW, interrupt request:

0

Activate IRQ request.

1

Do not activate IRQ request.

The processor treats nIRQ as level-sensitive. nIRQ must remain asserted until the processor acknowledges the interrupt.

This signal is only used when IRQ is in bypass mode, where it is used as legacy IRQ.

nFIQ[N:0]Input

Individual processor FIQ request input. Active-LOW, FIQ request:

0

Activate FIQ request.

1

Do not activate FIQ request.

The processor treats nFIQ as level-sensitive. nFIQ must remain asserted until the processor acknowledges the interrupt.

This signal is only used when FIQ is in bypass mode, where it is used as legacy FIQ.

nVIRQ[N:0]Input

Individual processor virtual IRQ request input. Active-LOW, virtual IRQ request:

0

Activate virtual IRQ request.

1

Do not activate virtual IRQ request.

The processor treats nVIRQ as level-sensitive. nVIRQ must remain asserted until the processor acknowledges the interrupt.

nVFIQ[N:0]Input

Individual processor virtual FIQ request input. Active-LOW, virtual FIQ request:

0

Activate virtual FIQ request.

1

Do not activate virtual FIQ request.

The processor treats nVFIQ as level-sensitive. nVFIQ must remain asserted until the processor acknowledges the interrupt.

nSEI[N:0]Input

Individual processor System Error Interrupt request. Active-LOW, SEI request:

0

Activate SEI request.

1

Do not activate SEI request.

The processor treats nSEI as edge-sensitive. The nSEI signal must be sent as a pulse to the processor.

nREI[N:0]Input

Individual processor RAM Error Interrupt request. Active-LOW, REI request.

0

Activate REI request. Reports an asynchronous RAM error in the system.

1

Do not activate REI request.

The processor treats nREI as edge-sensitive. nREI must be sent as a pulse to the processor.

nVSEI[N:0]Input

Individual processor virtual System Error Interrupt request. Active-LOW, virtual SEI request:

0

Activate virtual SEI request.

1

Do not activate virtual SEI request.

The processor treats nVSEI as edge-sensitive. nVSEI must be sent as a pulse to the processor.

nVCPUMNTIRQ[N:0]Output

Individual processor virtual CPU interface maintenance interrupt request. Processor N sets this signal LOW to issue a maintenance interrupt request to the external Distributor.

PERIPHBASE[43:18]Input

Specifies the base address for the GIC registers. This value is sampled into the Configuration Base Address Register (CBAR) at reset. See Configuration Base Address Register, EL1 and Configuration Base Address Register.

GICCDISABLEInput

Disables the GIC CPU interface logic and routes the legacy nIRQ, nFIQ, nVIRQ, and nVFIQ signals directly to the processor:

0

Enable the GIC CPU interface logic.

1

Disable the GIC CPU interface logic.

This signal is only sampled during powerup reset of the processor. See GICCDISABLE bypass mode for more information.

AXI4 Stream protocol signals: [a]
ICDTVALIDInputWhen HIGH it indicates that the Distributor is driving a valid transfer.
ICDTREADYOutputWhen HIGH it indicates that the processor can accept a transfer in the current cycle.
ICDTDATA[15:0]InputThe primary payload that passes data from the Distributor to the processor.
ICDTLASTInputWhen HIGH it indicates the boundary of a packet.
ICDTDEST[1:0]InputProvides routing information for the data stream from the Distributor.
ICCTVALIDOutputWhen HIGH it indicates that the processor is driving a valid transfer.
ICCTREADYInputWhen HIGH it indicates that the Distributor can accept a transfer in the current cycle.
ICCTDATA[15:0]OutputThe primary payload that passes data from the processor to the Distributor.
ICCTLASTOutputWhen HIGH it indicates the boundary of a packet.
ICCTID[1:0]OutputThe data stream identifier that indicates different streams of data.

[a] See the ARM® AMBA® AXI4-Stream™ Protocol Specification for more information.


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