8.3.6. Virtual CPU interface register summary

The virtual CPU interface forwards virtual interrupts to a connected Cortex-A57 MPCore multiprocessor, subject to the normal GIC handling and prioritization rules. The virtual interface control registers control virtual CPU interface operation, and in particular, the virtual CPU interface uses the contents of the List registers to determine when to signal virtual interrupts. When a processor accesses the virtual CPU interface, the List registers are updated. For more information on virtual CPU interface, see the ARM® Generic Interrupt Controller Architecture Specification, GICv3.

Table 8.14 shows the register map for the virtual CPU interface. The offsets in this table are relative to the virtual CPU interface block base address as shown in Table 8.1.

All the registers in Table 8.14 are word-accessible. Registers not described in this table are Reserved.

Table 8.14. Virtual CPU interface register summary

OffsetNameTypeResetDescription
0x0000GICV_CTLRRW0x00000000VM Control Register [a]
0x0004GICV_PMRRW0x00000000VM Priority Mask Register [a]
0x0008GICV_BPRRW0x00000002VM Binary Point Register [a]
0x000CGICV_IARRO0x000003FFVM Interrupt Acknowledge Register [a]
0x0010GICV_EOIRWO-VM End Of Interrupt Register [a]
0x0014GICV_RPRRO0x000000FFVM Running Priority Register [a]
0x0018GICV_HPPIRRO0x000003FFVM Highest Priority Pending Interrupt Register [a]
0x001CGICV_ABPRRW0x00000003VM Aliased Binary Point Register [a]
0x0020GICV_AIARRO0x000003FFVM Aliased Interrupt Acknowledge Register [a]
0x0024GICV_AEOIRWO-VM Aliased End of Interrupt Register [a]
0x0028GICV_AHPPIRRO0x000003FFVM Aliased Highest Priority Pending Interrupt Register [a]
0x002CGICV_STATUSRRW-VM Error Reporting Status Register [a]
0x00D0GICV_APR0RW0x00000000VM Active Priority Register
0x00FCGICV_IIDRRO0x0074043BVM CPU Interface Identification Register
0x1000GICV_DIRWO-VM Deactivate Interrupt Register [a]

[a] See the ARM® Generic Interrupt Controller Architecture Specification GICv3 for more information. The System register counterparts of these registers are described in the ARM® Generic Interrupt Controller Architecture Specification GICv3. The virtual CPU interface System registers do not have a separate encoding from the physical CPU interface System registers but access is controlled from the appropriate system controls that the ARM® Generic Interrupt Controller Architecture Specification GICv3 describes.


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