7.7.8. ACE supported transfers

For Normal Inner-Cacheable memory transfers initiated from one of the Cortex-A57 MPCore processors, the following transfers are supported on the ACE:

For Strongly-ordered or Device transactions initiated from one of the Cortex-A57 MPCore processors, the following transfers are supported on the ACE:

Table 7.6 describes the use of the burst types for Non-Cacheable and Cacheable but not allocated memory attributes.

Table 7.6. Use of WRAP and INCR burst types for Non-Cacheable and Cacheable but not allocated transactions

Burst type

Used by

WRAP

  • Non-Cacheable read transactions, excluding tablewalk or exclusive accesses.

  • Cacheable but not allocated read transactions initiated from one of the Cortex-A57 MPCore processors issued on AR-channel.

INCR

  • Non-cacheable tablewalk and exclusive read transactions.

  • Non-Cacheable or Cacheable but not allocated write transactions initiated from one of the Cortex-A57 MPCore processors issued on AW-channel.


If there are requests on the ACP interface, the following transfers can be generated on the ACE if comparable requests are received on the ACP:

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