6.4.7. Preload instruction behavior

The multiprocessor supports the PLD, PLDW, and PRFM prefetch hint instructions. For Normal Write-Back Cacheable memory page, the PLD, PLDW, and PRFM L1 instructions cause the line to be allocated to the L1 data cache of the executing processor. The PLD instruction brings the line into the cache in Exclusive or Shared state and the PLDW instruction brings the line into the cache in Exclusive state. The preload instruction cache, PLDI, is treated as a NOP. PLD and PLDW instructions are performance hints instructions only and might be dropped in some cases.

Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914