4.5.6. Architectural Feature Access Control Register

The CPACR characteristics are:

Purpose

Controls access to the CP10 and CP11 coprocessors. It also enables software to check for the presence of coprocessors CP10 to CP11.

Usage constraints

The accessibility to the CPACR by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RWRWRWRWRW

The CPACR has no effect on instructions executed in Hyp mode.

Configurations

The CPACR is:

Note

The NSACR controls Non-secure access to the CPACR fields. See Non-secure Access Control Register.

Attributes

See the register summary in Table 4.83.

Figure 4.83 shows the CPACR bit assignments.

Figure 4.83. CPACR bit assignments

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Table 4.117 shows the CPACR bit assignments.

Table 4.117. CPACR bit assignments

BitsNameFunction
[31]ASEDIS

Disables Advanced SIMD functionality:

0

All Advanced SIMD and FP instructions execute normally. This is the reset value.

1

All instruction encodings that are part of Advanced SIMD, but not FP instructions, are undefined.

[30:29]-

Reserved, res0.

[28]TRCDIS

Disable CP14 access to trace registers:

0

CP14 access to trace registers is not supported. This bit is res0.

[27:24]-

Reserved, res0.

[23:22]cp11

Defines the access rights for coprocessor 11. The values are:

0b00

Access denied. Any attempt to access the coprocessor generates an Undefined Instruction exception. This is the reset value.

0b01

Access at EL1 or higher only. Any attempt to access the coprocessor from software executing at EL0 generates an Undefined Instruction exception.

0b10

Reserved.

0b11

Full access. The meaning of full access is defined by the appropriate coprocessor.

If NSACR[11:10] is 0b00 in Non-secure state, these bits are res0.

[21:20]cp10

Defines the access rights for coprocessor 10. The values are:

0b00

Access denied. Any attempt to access the coprocessor generates an Undefined Instruction exception. This is the reset value.

0b01

Access at EL1 or higher only. Any attempt to access the coprocessor from software executing at EL0 generates an Undefined Instruction exception.

0b10

Reserved.

0b11

Full access. The meaning of full access is defined by the appropriate coprocessor.

If NSACR[11:10] is 0b00 in Non-secure state, these bits are res0.

[19:0]-

Reserved, res0.


Note

If the values of the cp11 and cp10 fields are not the same, the behavior is same as if both fields were set to the value of cp10, in all respects other than the value read back by explicitly reading cp11.

To access the CPACR in AArch32 state, read or write the CP15 register with:

MRC p15, 0, <Rt>, c1, c0, 2; Read Architectural Feature Access Control Register
MCR p15, 0, <Rt>, c1, c0, 2; Write Architectural Feature Access Control Register
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