4.5.2. TLB Type Register

The TLBTR characteristics are:

Purpose

Provides information about the TLB implementation.

Usage constraints

The accessibility to the TLBTR by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO
Configurations

The TLBTR is Common to Secure and Non-secure states.

Attributes

See the register summary in Table 4.82.

Figure 4.79 shows the TLBTR bit assignments.

Figure 4.79. TLBTR bit assignments

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Table 4.113 shows the TLBTR bit assignments.

Table 4.113. TLBTR bit assignments

BitsNameFunction
[31:1]-

Reserved, res0.

[0]nU

Not Unified. Indicates whether the implementation has a unified TLB. The value is:

0

Processor has a unified TLB.


To access the TLBTR in AArch32 state, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c0, 3; Read TLB Type Register
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