4.5.5. System Control Register

The SCTLR characteristics are:

Purpose

Provides the top-level control of the system, including its memory system.

Usage constraints

The accessibility to the SCTLR by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RWRWRWRWRW

Control bits in the SCTLR that are not applicable to a VMSA implementation read as the value that most closely reflects that implementation, and ignore writes.

Some bits in the register are read-only. These bits relate to non-configurable features of an implementation, and are provided for compatibility with other versions of the architecture.

Write access to the Secure copy of SCTLR is disabled when the CP15SDISABLE signal is HIGH.

Configurations

The SCTLR is Banked for Secure and Non-secure states.

The architectural mapping of the SCTLR is:

Attributes

See the register summary in Table 4.83.

Figure 4.82 shows the SCTLR bit assignments.

Figure 4.82. SCTLR bit assignments

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Table 4.116 shows the SCTLR bit assignments.

Table 4.116. SCTLR bit assignments

BitsNameAccessFunction
[31]--

Reserved, res0.

[30]TEBanked

Thumb Exception enable. This bit controls whether exceptions are taken in ARM or Thumb state:

0

Exceptions, including reset, taken in ARM state.

1

Exceptions, including reset, taken in Thumb state.

The primary input CFGTE defines the reset value of the TE bit of the Secure Banked register.

[29]AFEBanked

Access flag enable. This bit enables use of the AP[0] bit in the translation table descriptors as the Access flag. It also restricts access permissions in the translation table descriptors to the simplified model as described in the ARM® Architecture Reference Manual ARMv8. In the translation table descriptors, AP[0] is:

0

An access permissions bit. The full range of access permissions is supported. No access flag is implemented. This is the reset value.

1

The Access flag. Only the simplified model for access permissions is supported.

When TTBCR.EAE is set to 1, to enable use of the Long-descriptor translation table format, this bit is UNK/res1.

This bit is permitted to be cached in a TLB.

[28]TREBanked

TEX remap enable. This bit enables remapping of the TEX[2:1] bits for use as two translation table bits that can be managed by the operating system. Enabling this remapping also changes the scheme that describes the memory region attributes in the VMSA. The possible values are:

0

TEX remap disabled. TEX[2:0] are used, with the C and B bits, to describe the memory region attributes. This is the reset value.

1

TEX remap enabled. TEX[2:1] are reassigned for use as bits managed by the operating system. The TEX[0], C and B bits describe the memory region attributes, with the MMU remap registers.

When TTBCR.EAE is set to 1, to enable use of the Long-descriptor translation table format, this bit is UNK/res1.

This bit is permitted to be cached in a TLB.

[27:26]--

Reserved, res0.

[25]EEBanked

Exception Endianness. The value of this bit defines the value of the CPSR.E bit on entry to an exception vector, including reset. This value also indicates the endianness of the translation table data for translation table lookups. The values are:

0

Little endian.

1

Big endian.

The primary input CFGEND defines the reset value of the EE bit of the Secure Banked register.

[24]--

Reserved, res0.

[23:22]--

Reserved, res1.

[21]--

Reserved, res0.

[20]UWXNBanked

Unprivileged write permission implies EL1 Execute Never (XN). You can use this bit to require all memory regions with unprivileged write permissions are treated as XN for accesses from software executing at EL1. Regions with unprivileged write permission are:

0

Not forced to be XN. This is the reset value.

1

Forced to be XN for accesses from software executing at EL1.

This bit is permitted to be cached in a TLB.

[19]WXNBanked

Write permission implies Execute Never (XN). You can use this bit to require all memory regions with write permissions are treated as XN. Regions with write permission are:

0

Not forced to be XN. This is the reset value.

1

Forced to be XN.

This bit is permitted to be cached in a TLB.

[18]nTWEBanked

WFE trap. The values are:

0

A WFE instruction executed at EL0 that causes suspended execution as if the event register is not set and there is no pending WFE wake-up event. It is treated as undefined.

1

WFE instructions executed as normal. This is the reset value.

[17]--

Reserved, res0.

[16]nTWIBanked

WFI trap. The values are:

0

A WFI instruction executed at EL0 that causes suspended execution as if there is not a pending WFI wake-up event. It is treated as undefined.

1

WFE instructions executed as normal. This is the reset value.

[15:14]--

Reserved, res0.

[13]VBanked

Vectors bit. This bit selects the base address of the exception vectors:

0

Normal exception vectors, base address 0x00000000. This base address can be remapped.

1

High exception vectors, base address 0xFFFF0000. This base address is never remapped.

The primary input VINITHI defines the reset value of the V bit of the Secure Banked register.

[12]IBanked

Instruction Cache enable. This is a global enable bit for Instruction Caches:

0

Instruction Caches disabled. This is the reset value.

1

Instruction Caches enabled.

[11]--Reserved, res1.
[10:9]--

Reserved, res0.

[8]SEDBanked

SETEND instruction disable. The values are:

0

SETEND instruction is enabled. This is the reset value.

1

SETEND instruction is unallocated.

[7]ITDBanked

IT instruction disable. The values are:

0

IT instruction functionality is enabled. This is the reset value.

1

All encodings of the IT instruction are undefined when either:

  • hw[3:0] are not equal to 0b1000.

  • IT instructions with a subsequent 32-bit instruction.

  • Subsequent PC reading or writing instruction.

[6]THEEBanked

ThumbEE enable. This value is:

0

ThumbEE is not implemented.

[5]CP15BENBanked

AArch32 CP15 barrier enable. The values are:

0

CP15 barrier operations disabled. Their encodings are undefined.

1

CP15 barrier operations enabled. This is the reset value.

[4:3]--

Reserved, res1.

[2]CBanked

Cache enable. This is a global enable bit for data and unified caches:

0

Data and unified caches disabled. This is the reset value.

1

Data and unified caches enabled.

[1]ABanked

Alignment check enable. This is the enable bit for Alignment fault checking:

0

Alignment fault checking disabled. This is the reset value.

1

Alignment fault checking enabled.

[0]MBanked

MMU enable. This is a global enable bit for the EL1 and EL0 stage 1 MMU:

0

EL1 and EL0 stage 1 MMU disabled. This is the reset value.

1

EL1 and EL0 stage 1 MMU enabled.


To access the SCTLR in AArch32 state, read or write the CP15 register with:

MRC p15, 0, <Rt>, c1, c0, 0; Read System Control Register
MCR p15, 0, <Rt>, c1, c0, 0; Write System Control Register

To access the SCTLR_EL1 in AArch64 state, read or write the register with:

MRS <Xt>, SCTLR_EL1; Read System Control Register
MSR SCTLR_EL1, <Xt>; Write System Control Register

To access the SCTLR_EL3 in AArch64 state, read or write the register with:

MRS <Xt>, SCTLR_EL3; Read System Control Register
MSR SCTLR_EL3, <Xt>; Write System Control Register
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