7.4. L2 cache prefetcher

The Cortex-A57 MPCore multiprocessor includes a hardware L2 prefetcher. Some of the key features are:

You can program the CPUECTLR register to indicate the maximum number of prefetches to be allocated in the PRQ on the following:

See CPU Extended Control Register, EL1 for more information.

The programmed distance is also used as the skip distance for any load-store or instruction fetch read with a stride match that hits in the L2 cache. In these cases, a single prefetch request is allocated in the PRQ as:

prefetch address = current address + (stride x programmed distance)

Note

The stride for an instruction fetch access is always one cache line.

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