6.4.1. Behavior for different memory types

The L1 data memory system uses memory attributes from the MMU to determine the behaviors of memory transactions to regions of memory. See Chapter 5 Memory Management Unit for more information.

The L1 data memory system uses the following memory types:

Note

Some attribute combinations are only available if the LPAE page table format is used.

Table 6.1 shows the memory attribute combinations available.

Table 6.1. Memory attribute combinations

Outer MemAttrInner MemAttrCortex-A57 MPCore multiprocessor internal memory type
DevicenGnRnEDevice nGnRnE
DevicenGnREDevice nGnRE
DevicenGREDevice nGRE
DeviceGREDevice GRE
Non-cacheableNon-cacheableNon-cacheable
Non-cacheableWrite-ThroughNon-cacheable
Non-cacheableWrite-BackNon-cacheable
Write-ThroughNon-cacheableNon-cacheable
Write-ThroughWrite-ThroughNon-cacheable
Write-ThroughWrite-BackNon-cacheable
Write-BackNon-cacheableNon-cacheable
Write-BackWrite-ThroughNon-cacheable
Write-BackWrite-Back No-AllocateWrite-Back No-Allocate
Write-BackWrite-Back Read-AllocateWrite-Back Read-Write-Allocate
Write-BackWrite-Back Write-AllocateWrite-Back Read-Write-Allocate
Write-BackWrite-Back Read-Write-AllocateWrite-Back Read-Write-Allocate

The L1 and L2 data memory system use the internal memory type to determine its behavior in addition to the value of the ARCACHE, AWCACHE, and TXREQFLIT[MemAttr] signals. The L1 and L2 caches use allocation hints from the inner memory attributes and the ARCACHE, AWCACHE, and TXREQ[MemAttr] signals use allocation hints from the outer memory attributes.

Note

The Cortex-A57 MPCore multiprocessor provides the raw memory attributes from the MMU on external signals. See ACE and CHI interface signals for more information.

If any memory instruction crosses a 4KB page boundary between two pages with different memory types such as Normal and Device memory, the result is unpredictable and an abort might be triggered or incorrect data delivered.

If any given Physical Address is mapped to Virtual Addresses with different memory types or different cacheability such as Non-cacheable, Write-Through, or Write-Back, the result is unpredictable. This can occur if two Virtual Addresses are mapped to the same Physical Address at the same time with different memory type or cacheability, or if the same Virtual Address has its memory type or cacheability changed over time without the appropriate cache cleaning or barriers.

Write-Back Read-Write-Allocate

This is expected to be the most common and highest performance memory type. Any read or write to this memory type searches the cache to determine if the line is resident. If it is, the line is read or updated. A store that hits a Write-Back cache line does not update main memory.

If the required cache line is not in the cache, one or more cache lines is requested from the L2 cache. The L2 cache can obtain the lines from its cache, from another coherent L1 cache, or from memory. The line is then placed in the L1 cache, and the operation completes from the L1 cache.

Write-Back No-Allocate

Use Write-Back No-Allocate memory to access data that might be in the cache because other virtual pages that are mapped to the same Physical Address are Write-Back Read-Write-Allocate. Write-Back No-Allocate memory avoids polluting the caches when accessing large memory structures that are used only one time. The cache is searched and the correct data is delivered or updated if the data resides in one of the caches. However, if the request misses the L1 or L2 cache, the line is not allocated into that cache. For a read that misses all caches, the required data is read to satisfy the memory request, but the line is not added to the cache. For a write that misses in all caches, the modified bytes are updated in memory.

Note

The No-Allocate allocation hint is only a performance hint. The processor might in some cases, allocate Write-Back No-Allocate lines into the L1 data cache or the L2.

Write-Through

The multiprocessor memory system treats all Write-Through pages as Non-cacheable.

Non-cacheable

Normal Non-cacheable memory is not looked up in any cache. The requests are sent directly to memory. Read requests might over-read in memory, for example, reading 64 bytes of memory for a 4-byte access, and a single external memory access might satisfy multiple memory requests. Write requests might merge with other write requests to the same bytes or nearby bytes.

Device

Device memory types are used for communicating with input and output devices and memory-mapped peripherals. They are not looked up in any cache.

All the memory operations for a single instruction can be sent to the interconnect as multiple naturally aligned requests.

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