ARM Cortex-A57 MPCore Processor Technical Reference Manual: B.1.1. Use of R15 by instruction

B.1.1. Use of R15 by instruction

The Cortex-A57 MPCore processor does not implement a Read 0 policy on unpredictable use of R15 by instruction. Instead, the processor reads the PC with the standard offset that applies for the current instruction set with alignment to a word boundary.

Word-alignment of the PC is imposed for all T32 instructions that are either:

Defined as loads in the definition of PMU event 0x70.
Defined as stores in the definition of PMU event 0x71.

With the notable exceptions to this alignment policy that:

The PC value for TBB & TBH instructions is explicitly not forced to a word-aligned value. TBB and TBH are technically PMU loads but for the processor to comply with the architecture, it cannot force the PC to a word-aligned value for these instructions.
The PC value for ADR instructions is explicitly forced to a word-aligned value. ADR is not a PMU load or a PMU store, but the architecture specifies word-aligned PC for ADR instructions.

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