10.8.9. Debug Component Identification Registers

There are four read-only Debug Component Identification Registers, Component ID0 through Component ID3. Table 10.24 shows these registers.

Table 10.24. Summary of the Debug Component Identification Registers

RegisterValueOffset
Component ID00x0D0xFF0
Component ID10x900xFF4
Component ID20x050xFF8
Component ID30xB10xFFC

The Debug Component Identification Registers identify Debug as an ARM Debug Interface v5 component. The Debug Component ID registers are:

Debug Component Identification Register 0

The EDCIDR0 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The EDCIDR0 is in the Debug power domain.

Attributes

See the register summary in Table 10.10.

Figure 10.19 shows the EDCIDR0 bit assignments.

Figure 10.19. EDCIDR0 bit assignments

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Table 10.25 shows the EDCIDR0 bit assignments.

Table 10.25. EDCIDR0 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:0]PRMBL_0
0x0D

Preamble byte 0.


Debug Component Identification Register 1

The EDCIDR1 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The EDCIDR1 is in the Debug power domain.

Attributes

See the register summary in Table 10.10.

Figure 10.20 shows the EDCIDR1 bit assignments.

Figure 10.20. EDCIDR1 bit assignments

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Table 10.26 shows the EDCIDR1 bit assignments.

Table 10.26. EDCIDR1 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]CLASS
0x9

Debug component.

[3:0]PRMBL_1
0x0

Preamble.


Debug Component Identification Register 2

The EDCIDR2 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The EDCIDR2 is in the Debug power domain.

Attributes

See the register summary in Table 10.10.

Figure 10.21 shows the EDCIDR2 bit assignments.

Figure 10.21. EDCIDR2 bit assignments

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Table 10.27 shows the EDCIDR2 bit assignments.

Table 10.27. EDCIDR2 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:0]PRMBL_2
0x05

Preamble byte 2.


Debug Component Identification Register 3

The EDCIDR3 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The EDCIDR3 is in the Debug power domain.

Attributes

See the register summary in Table 10.10.

Figure 10.22 shows the EDCIDR3 bit assignments.

Figure 10.22. EDCIDR3 bit assignments

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Table 10.28 shows the EDCIDR3 bit assignments.

Table 10.28. EDCIDR3 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:0]PRMBL_3
0xB1

Preamble byte 3.


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