10.8.1. External Debug Reserve Control Register

The EDRCR characteristics are:

Purpose

Used to cancel bus requests and clear sticky bits in the EDSCR.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
ERRORERRORERROR-WIWO

Table 10.1 describes the access conditions.

Configurations

The EDRCR is in the Core power domain.

Attributes

See the register summary in Table 10.10.

Figure 10.7 shows the EDRCR bit assignments.

Figure 10.7. EDRCR bit assignments

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Table 10.11 shows the EDRCR bit assignments.

Table 10.11. EDRCR bit assignments

BitsNameFunction
[31:5]-

Reserved, res0.

[4]CBRRQ

Reserved.res0.

[3]CSPA

Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The possible values are:

0

No action.

1

Clear the EDSCR.PipeAdv bit to 0.

[2]CSE

Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The possible values:

0

No action.

1

Clear the EDSCR.{TXU, RXO, ERR} bits, and, if the processor is in Debug state, the EDSCR.ITO bit, to 0.

[1:0]-

Reserved, res0.


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