10.8.8. Debug Peripheral Identification Registers

The Debug Peripheral Identification Registers provide standard information required for all components that conform to the ARM® Debug Interface Architecture Specification ADIv5.0 to ADIv5.2. They are a set of eight registers, listed in register number order in Table 10.18.

Table 10.18. Summary of the Debug Peripheral Identification Registers

RegisterValueOffset
EDPIDR40x040xFD0
EDPIDR50x000xFD4
EDPIDR60x000xFD8
EDPIDR70x000xFDC
EDPIDR00x070xFE0
EDPIDR10xBD0xFE4
EDPIDR20x2B0xFE8
EDPIDR30x000xFEC

Only bits[7:0] of each Debug Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Debug Peripheral ID Registers define a single 64-bit Peripheral ID.

The Debug Peripheral ID registers are:

Debug Peripheral Identification Register 0

The EDPIDR0 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The EDPIDR0 is in the Debug power domain.

Attributes

See the register summary in Table 10.10.

Figure 10.14 shows the EDPIDR0 bit assignments.

Figure 10.14. EDPIDR0 bit assignments

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Table 10.19 shows the EDPIDR0 bit assignments.

Table 10.19. EDPIDR0 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:0]Part_0
0x07

Least significant byte of the debug part number.


Debug Peripheral Identification Register 1

The EDPIDR1 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The EDPIDR1 is in the Debug power domain.

Attributes

See the register summary in Table 10.10.

Figure 10.15 shows the EDPIDR1 bit assignments.

Figure 10.15. EDPIDR1 bit assignments

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Table 10.20 shows the EDPIDR1 bit assignments.

Table 10.20. EDPIDR1 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]DES_0
0xB

ARM Limited. This is the least significant nibble of JEP106 ID code.

[3:0]Part_1
0xD

Most significant nibble of the debug part number.


Debug Peripheral Identification Register 2

The EDPIDR2 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The EDPIDR2 is in the Debug power domain.

Attributes

See the register summary in Table 10.10.

Figure 10.16 shows the EDPIDR2 bit assignments.

Figure 10.16. EDPIDR2 bit assignments

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Table 10.21 shows the EDPIDR2 bit assignments.

Table 10.21. EDPIDR2 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]Revision
0x2

Part major revision.

[3]JEDEC
0b1

RAO. Indicates a JEP106 identity code is used.

[2:0]DES_1
0b011

ARM Limited. This is the most significant nibble of JEP106 ID code.


Debug Peripheral Identification Register 3

The EDPIDR3 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The EDPIDR3 is in the Debug power domain.

Attributes

See the register summary in Table 10.10.

Figure 10.17 shows the EDPIDR3 bit assignments.

Figure 10.17. EDPIDR3 bit assignments

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Table 10.22 shows the EDPIDR3 bit assignments.

Table 10.22. EDPIDR3 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]REVAND
0x0

Part minor revision.

[3:0]CMOD
0x0

Customer modified.


Debug Peripheral Identification Register 4

The EDPIDR4 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The EDPIDR4 is in the Debug power domain.

Attributes

See the register summary in Table 10.10.

Figure 10.18 shows the EDPIDR4 bit assignments.

Figure 10.18. EDPIDR4 bit assignments

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Table 10.23 shows the EDPIDR4 bit assignments.

Table 10.23. EDPIDR4 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]Size
0x0

Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the Debug Component ID registers.

[3:0]DES_2
0x4

ARM Limited. This is the least significant nibble JEP106 continuation code.


Debug Peripheral Identification Register 5-7

No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are res0.

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