10.11.4. ROM table Debug Peripheral Identification Registers

The Debug Peripheral Identification Registers provide standard information required for all components that conform to the ARM® Debug Interface Architecture Specification ADIv5.0 to ADIv5.2. There is a set of eight registers, listed in register number order in Table 10.33.

Table 10.33. Summary of the ROM table Debug Peripheral Identification Registers

RegisterValueOffset
ROMPID40x040xFD0
ROMPID50x000xFD4
ROMPID60x000xFD8
ROMPID70x000xFDC
ROMPID00xA20xFE0
ROMPID10xB40xFE4
ROMPID20x2B0xFE8
ROMPID30x000xFEC

Only bits[7:0] of each ROM table Debug Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight ROM table Debug Peripheral ID Registers define a single 64-bit Peripheral ID.

The ROM table Debug Peripheral ID registers are:

ROM table Debug Peripheral Identification Register 0

The ROMPIDR0 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The ROMPIDR0 is in the Debug power domain.

Attributes

See the register summary in Table 10.30.

Figure 10.25 shows the ROMPIDR0 bit assignments.

Figure 10.25. ROMPIDR0 bit assignments

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Table 10.34 shows the ROMPIDR0 bit assignments.

Table 10.34. ROMPIDR0 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:0]Part_0
0xA2

Least significant byte of the ROM table part number.


ROM table Debug Peripheral Identification Register 1

The ROMPIDR1 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The ROMPIDR1 is in the Debug power domain.

Attributes

See the register summary in Table 10.30.

Figure 10.26 shows the ROMPIDR1 bit assignments.

Figure 10.26. ROMPIDR1 bit assignments

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Table 10.35 shows the ROMPIDR1 bit assignments.

Table 10.35. ROMPIDR1 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]DES_0
0xB

Least significant nibble of JEP106 ID code. For ARM Limited.

[3:0]Part_1
0x4

Most significant nibble of the ROM table part number.


ROM table Debug Peripheral Identification Register 2

The ROMPIDR2 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The ROMPIDR2 is in the Debug power domain.

Attributes

See the register summary in Table 10.30.

Figure 10.27 shows the ROMPIDR2 bit assignments.

Figure 10.27. ROMPIDR2 bit assignments

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Table 10.36 shows the ROMPIDR2 bit assignments.

Table 10.36. ROMPIDR2 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]Revision
0x2

Part major revision.

[3]JEDEC
0b1

RAO. Indicates a JEP106 identity code is used.

[2:0]DES_1
0b011

Designer, most significant bits of JEP106 ID code. For ARM Limited.


ROM table Debug Peripheral Identification Register 3

The ROMPIDR3 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The ROMPIDR3 is in the Debug power domain.

Attributes

See the register summary in Table 10.30.

Figure 10.28 shows the ROMPIDR3 bit assignments.

Figure 10.28. ROMPIDR3 bit assignments

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Table 10.37 shows the ROMPIDR3 bit assignments.

Table 10.37. ROMPIDR3 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]REVAND
0x0

Part minor revision.

[3:0]CMOD
0x0

Customer modified.


ROM table Debug Peripheral Identification Register 4

The ROMPIDR4 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The ROMPIDR4 is in the Debug power domain.

Attributes

See the register summary in Table 10.30.

Figure 10.29 shows the ROMPIDR4 bit assignments.

Figure 10.29. ROMPIDR4 bit assignments

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Table 10.38 shows the ROMPIDR4 bit assignments.

Table 10.38. ROMPIDR4 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]Size
0x0

Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the Debug Component ID registers.

[3:0]DES_2
0x4

Designer, JEP106 continuation code, least significant nibble. For ARM Limited.


ROM table Debug Peripheral Identification Register 5-7

No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are res0.

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