12.5. Cross trigger register summary

This section describes the cross trigger registers in the Cortex-A57 MPCore multiprocessor. These registers are accessed through the internal memory-mapped interface or the external debug interface.

Table 12.3 shows the cross trigger registers in the Cortex-A57 MPCore multiprocessor.

Table 12.3. Cross trigger register summary

OffsetNameTypeWidthDescription
0x000CTICONTROLRW32-bitCTI Control register [a]
0x000-0x00C---Reserved
0x010CTIINTACKWO32-bitCTI Output Trigger Acknowledge register [a]
0x014CTIAPPSETRW32-bitCTI Application Trigger Set register [a]
0x018CTIAPPCLEARWO32-bitCTI Application Trigger Clear register [a]
0x01CCTIAPPPULSEWO32-bitCTI Application Pulse register [a]
0x020CTIINEN0RW32-bitCTI Input Trigger to Output Channel Enable registers [a]
0x024CTIINEN1
0x028CTIINEN2
0x02CCTIINEN3
0x030CTIINEN4
0x034CTIINEN5
0x038CTIINEN6
0x03CCTIINEN7
0x040-0x09C---Reserved
0x0A0CTIOUTEN0RW32-bitCTI Input Channel to Output Trigger Enable registers [a]
0x0A4CTIOUTEN1
0x0A8CTIOUTEN2
0x0ACCTIOUTEN3
0x0B0CTIOUTEN4
0x0B4CTIOUTEN5
0x0B8CTIOUTEN6
0x0BCCTIOUTEN7
0x0C0-0x12C---Reserved
0x130CTITRIGINSTATUSRO32-bitCTI Trigger In Status register [a]
0x134CTITRIGOUTSTATUSRO32-bitCTI Trigger Out Status register [a]
0x138CTICHINSTATUSRO32-bitCTI Channel In Status register [a]
0x13CCTICHOUTSTATUSRO32-bitCTI Channel Out Status register [a]
0x140CTIGATERW32-bitCTI Channel Gate Enable register [a]
0x144-0xED8---Reserved
0xEDCCTIITCHINACKWO32-bitCTI Integration Test Channel In Acknowledge register
0xEE0CTIITTRIGINACKWO32-bitCTI Integration Test Trigger In Acknowledge register
0xEE4CTIITCHOUTWO32-bitCTI Integration Test Channel Out register
0xEE8CTIITTRIGOUTWO32-bitCTI Integration Test Trigger Out register
0xEECCTIITCHOUTACKRO32-bitCTI Integration Test Channel Out Acknowledge register
0xEF0CTIITTRIGOUTACKRO32-bitCTI Integration Test Trigger Out Acknowledge register
0xEF4CTIITCHINRO32-bitCTI Integration Test Channel In register
0xEF8CTIITTRIGINRO32-bitCTI Integration Test Trigger In register
0xEFC-0xF7C---Reserved
0xF00CTIICTRLRW32-bitCTI Integration Mode Control register
0xF04-0xFAC---Reserved
0xFB0CTILARWO32-bitCTI Lock Access Register [a]
0xFB4CTILSRRO32-bitCTI Lock Status Register [a]
0xFB8CTIAUTHSTATUSRO32-bitCTI Authentication Status register [a]
0xFBC-0xFC4---Reserved
0xFC8CTIDEVIDRO32-bitCTI Device Identification register
0xFCCCTIDEVTYPERO32-bitCTI Device Type register [a]
0xFD0CTIPIDR4RO32-bitCTI Peripheral Identification Register 4
0xFD4CTIPIDR5RO32-bitCTI Peripheral Identification Register 5-7
0xFD8CTIPIDR6
0xFDCCTIPIDR7
0xFE0CTIPIDR0RO32-bitCTI Peripheral Identification Register 0
0xFE4CTIPIDR1RO32-bitCTI Peripheral Identification Register 1
0xFE8CTIPIDR2RO32-bitCTI Peripheral Identification Register 2
0xFECCTIPIDR3RO32-bitCTI Peripheral Identification Register 3
0xFF0CTICIDR0RO32-bitCTI Component Identification Register 0
0xFF4CTICIDR1RO32-bitCTI Component Identification Register 1
0xFF8CTICIDR2RO32-bitCTI Component Identification Register 2
0xFFCCTICIDR3RO32-bitCTI Component Identification Register 3

[a] See the ARM® Architecture Reference Manual ARMv8 for more information.


Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914