8.2.1. GIC memory map

The GIC registers are memory-mapped, with a physical base address specified by PERIPHBASE[43:18]. This input must be tied to a constant value. The PERIPHBASE value is sampled during reset into the Configuration Base Address Register (CBAR) for each processor in the MPCore device. See Configuration Base Address Register, EL1 and Configuration Base Address Register.

The GIC registers are grouped into three contiguous 64KB pages. These blocks include the CPU interface, virtual interface control, and virtual CPU interface blocks.

Memory regions used for these registers must be marked as Device, nGnRnE, nGnRE, nGRE, or GRE in the translation tables. Memory regions marked as Normal memory cannot access any of the GIC registers, but can access caches or external memory as required.

Access to these registers must be with the single word load and store instructions. Load/store-multiple, load/store-double, and load/store exclusive instructions result in a Data Abort exception to the requesting processor.

The Accelerator Coherency Port (ACP) cannot access any of the GIC registers. The registers must be accessed through one of the processors. Any access from ACP to the GIC registers goes to external memory and no Data Abort exception is generated.

Table 8.1 shows the GIC memory map of a Cortex-A57 MPCore processor. An external standalone GIC such as the ARM GIC-400 or other proprietary GIC might differ. It lists the address offsets for the GIC blocks relative to the PERIPHBASE base address.

Table 8.1. Cortex-A57 MPCore multiprocessor GIC memory map

Offset range from PERIPHBASE[43:18]

GIC block


CPU interface




Virtual interface control




Virtual CPU interface (4KB page offset)




Alias of the Virtual CPU interface (64KB page offset alias)



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