5.6. Intermediate table walk caches

The Cortex-A57 MPCore multiprocessor implements dedicated caches that store intermediate levels of translation table entries as part of a table walk. Cached entries are associated with an ASID and a VMID where applicable for Non-secure EL1 translations.

Care is required when using the reserved ASID method for context switch. See the ARM® Architecture Reference Manual ARMv8 for more information.

Example 5.1 shows how to synchronize ASID and TTBR changes using a reserved ASID.

Example 5.1. Using a reserved ASID to synchronize ASID and TTBR changes

In this example, the operating system uses a particular reserved ASID value for the synchronization of the ASID and the Translation Table Base Register. You can use this approach only when the size of the mapping for any given Virtual Address is the same in the old and new translation tables. The example uses the value of 0.

The software uses the following sequences that must be executed from memory marked as global:

Change ASID to 0
Change Translation Table Base Register
Change ASID to new value

If the code relies on only leaf translation table entries that are cached, it can incorrectly assume that entries tagged with the reserved ASID are not required to be flushed. For example:

The incorrect assumption leads to the following failure:


When you use a reserved ASID, you must invalidate the TLB to deallocate the translation table memory.

Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D