11.5. AArch32 PMU register summary

The PMU counters and their associated control registers are accessible in AArch32 state from the System registers with MCR and MRC instructions for 32-bit registers and MCRR and MRRC for 64-bit registers.

Table 11.6 gives a summary of the PMU registers in AArch32 state.

Table 11.6 also shows the offset address for the AArch32 registers that are accessible from the internal memory-mapped interface or the external debug interface.

See the Memory-mapped register summary for a complete list of registers that are accessible from the internal memory-mapped interface or the external debug interface.

Table 11.6. PMU register summary in AArch32 state

OffsetCRnop1CRmop2NameTypeWidthDescription
0xE04c90c120PMCRRW32-bitPerformance Monitors Control Register, EL0
0xC00  1PMCNTENSETRW32-bitPerformance Monitors Count Enable Set Register [a]
0xC20  2PMCNTENCLRRW32-bitPerformance Monitors Count Enable Clear Register [a]
0xC80  3PMOVSRRW32-bitPerformance Monitors Overflow Flag Status Register [a]
0xCA0  4PMSWINCWO32-bitPerformance Monitors Software Increment Register [a]
-  5PMSELRRW32-bitPerformance Monitors Event Counter Selection Register [a]
0xE20  6PMCEID0RO32-bitPerformance Monitors Common Event Identification Register 0, EL0
0xE24  7PMCEID1RO32-bitPerformance Monitors Common Event Identification Register 1 [a]
0x0F8c90c130PMCCNTR[31:0]RW32-bitPerformance Monitors Cycle Count Register [a]
0x0FC----PMCCNTR[63:32]
--0c9-PMCCNTR[63:0]64-bit
-c90c131PMXEVTYPERRW32-bitPerformance Monitors Selected Event Type Register [a]
0x47C   PMCCFILTRRW32-bitPerformance Monitors Cycle Count Filter Register [a]
-c90c132PMXEVCNTRRW32-bitPerformance Monitors Selected Event Count Register [a]
-  c140PMUSERENRRW32-bitPerformance Monitors User Enable Register [a]
0xC40  1PMINTENSETRW32-bitPerformance Monitors Interrupt Enable Set Register [a]
0xC60  2PMINTENCLRRW32-bitPerformance Monitors Interrupt Enable Clear Register [a]
0xCC0  3PMOVSSETRW32-bitPerformance Monitors Overflow Flag Status Set Register [a]
0x000c140c80PMEVCNTR0RW32-bitPerformance Monitors Event Count Registers [a]
0x008  1PMEVCNTR1
0x010  2PMEVCNTR2
0x018  3PMEVCNTR3
0x020  4PMEVCNTR4
0x028  5PMEVCNTR5
0x400  c120PMEVTYPER0RW32-bitPerformance Monitors Event Type Registers [a]
0x404  1PMEVTYPER1
0x408  2PMEVTYPER2
0x40C  3PMEVTYPER3
0x410  4PMEVTYPER4
0x414  5PMEVTYPER5
0x47C  c157PMCCFILTRRW32-bitPerformance Monitors Cycle Count Filter Register [a]

[a] See the ARM® Architecture Reference Manual ARMv8 for more information.


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