11.7.11. Performance Monitors Configuration Register

The PMCFGR characteristics are:

Purpose

Contains PMU specific configuration data.

Usage constraints

The accessibility to the PMCFGR by condition code is:

OffDLKOSLKEPMADSLKDefault
ErrorErrorErrorErrorRORO

Table 11.1 describes the condition codes.

Configurations

The PMCFGR is in the Core power domain.

Attributes

See the register summary in Table 11.7.

Figure 11.8 shows the PMCFGR bit assignments.

Figure 11.8. PMCFGR bit assignments

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Table 11.12 shows the PMCFGR bit assignments.

Table 11.12. PMCFGR bit assignments

BitsNameFunction
[31:17]-

Reserved, res0.

[16]EX

Export supported. The value is:

1

Export is supported. PMCR_EL0.EX is read/write.

[15]CCD

Cycle counter has pre-scale. The value is:

1

PMCR_EL0.D is read/write.

[14]CC

Dedicated cycle counter supported. The value is:

1

Dedicated cycle counter is supported.

[13:8]Size

Counter size. The value is:

0b111111

64-bit counters.

[7:0]N

Number of event counters. The value is:

0x06

Six counters.


The PMCFGR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xE00.

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