11.3. AArch64 PMU register summary

The PMU counters and their associated control registers are accessible in AArch64 state with MRS and MSR instructions.

Table 11.3 shows the PMU registers in AArch64 state. It also shows the offset address for the registers that are accessible from the internal memory-mapped interface or the external debug interface.

Table 11.3. PMU register summary in AArch64 state

OffsetNameTypeWidthDescription
0xE04PMCR_EL0RW32-bitPerformance Monitors Control Register, EL0
0xC00PMCNTENSET_EL0RW32-bitPerformance Monitors Count Enable Set Register [a]
0xC20PMCNTENCLR_EL0RW32-bitPerformance Monitors Count Enable Clear Register [a]
0xC80PMOVSCLR_EL0RW32-bitPerformance Monitors Overflow Flag Status Register [a]
0xCA0PMSWINC_EL0WO32-bitPerformance Monitors Software Increment Register [a]
-PMSELR_EL0RW32-bitPerformance Monitors Event Counter Selection Register [a]
0xE20PMCEID0_EL0RO32-bitPerformance Monitors Common Event Identification Register 0, EL0
0xE24PMCEID1_EL0RO32-bitPerformance Monitors Common Event ID Register 1 [a]
-PMCCNTR_EL0RW64-bitPerformance Monitors Cycle Count Register [a]
-PMXEVTYPER_EL0RW32-bitPerformance Monitors Selected Event Type Register [a]
0x47CPMCCFILTR_EL0RW32-bitPerformance Monitors Cycle Count Filter Register [a] [b]
-PMXEVCNTR0_EL0RW32-bitPerformance Monitors Selected Event Count Register [a]
-PMUSERENR_EL0RW32-bitPerformance Monitors User Enable Register [a]
0xC40PMINTENSET_EL1RW32-bitPerformance Monitors Interrupt Enable Set Register [a]
0xC60PMINTENCLR_EL1RW32-bitPerformance Monitors Interrupt Enable Clear Register [a]
0xCC0PMOVSSET_EL0RW32-bitPerformance Monitors Overflow Flag Status Set Register [a]
0x000PMEVCNTR0_EL0RW32-bitPerformance Monitors Event Count Registers [a]
0x008PMEVCNTR1_EL0
0x010PMEVCNTR2_EL0
0x018PMEVCNTR3_EL0
0x020PMEVCNTR4_EL0
0x028PMEVCNTR5_EL0
0x400PMEVTYPER0_EL0RW32-bitPerformance Monitors Event Type Registers [a]
0x404PMEVTYPER1_EL0
0x408PMEVTYPER2_EL0
0x40CPMEVTYPER3_EL0
0x410PMEVTYPER4_EL0
0x414PMEVTYPER5_EL0
0x47CPMCCFILTR_EL0RW32-bitPerformance Monitors Cycle Count Filter Register [a]

[a] See the ARM® Architecture Reference Manual ARMv8 for more information.

[b] The CP15 encoding provides access to PMCCFILTR_EL0 only when PMSELR_EL0.SEL==31.


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